[PATCH v8 02/15] drm/sun4i: tcon: Compute DCLK dividers based on format, lanes

[Jagan Teki]

On Tue, Mar 19, 2019 at 4:23 PM Maxime Ripard <maxime.ripard at bootlin.com> wrote:
>
> On Mon, Mar 11, 2019 at 09:36:27PM +0530, Jagan Teki wrote:
> > On Mon, Mar 11, 2019 at 9:08 PM Maxime Ripard <maxime.ripard at bootlin.com> wrote:
> > >
> > > On Mon, Mar 11, 2019 at 07:06:24PM +0530, Jagan Teki wrote:
> > > > pll-video => pll-mipi => tcon0 => tcon0-pixel-clock is the typical
> > > > MIPI clock topology in Allwinner DSI controller.
> > > >
> > > > TCON dotclock driver is computing the desired DCLK divider based on
> > > > panel pixel clock along with input DCLK min, max divider values from
> > > > tcon driver and that would eventually set the pll-mipi clock rate.
> > > >
> > > > The current code allows the TCON clock divider to have a default 4
> > > > for min, max ranges that would fail to compute the desired pll-mipi
> > > > rate while supporting new panels.
> > > >
> > > > So, add the computation logic 'format/lanes' to dclk min and max dividers
> > > > and instead of default 4. This computation logic align with Allwinner A64
> > > > BSP, hoping that would work even for A33.
> > >
> > > Last time we discussed this, we found out that this wasn't the case,
> > > even in the BSP.
> >
> > This was the case for BSP to compute pll-mipi not for TCON_DSI clock
> > register, SUN4I_TCON0_DCLK_REG, which marked the divider 4 by default.
> >
> > > What compelling evidence have you found that makes you say otherwise?
> >
> > divider 4 isn't worked, this I would mentioned before as well.
>
> Maybe you mentionned it before, but it's nowhere to be found in your
> commit log.

I have added it in 3rd paragraph in commit message, may be you missed
it or you may look for different text.

"The current code allows the TCON clock divider to have a default 4
for min, max ranges that would fail to compute the desired pll-mipi
rate while supporting new panels."

>
> > Tested this on 4 different panels, and below are the desired divider values
> > and pll-mipi clock rate with respect to pixel clock frequency.
> >
> > - 55MHz pixel clock with 4-lane panel, and the desired DSI clock divider
> >   is 6 with the output parent clock rate of 330MHz.
> > - 30MHz pixel clock with 4-lane panel, and the desired DSI clock divider
> >   is 6 with parent clock rate of 180MHz.
> > - 27.5Mhz pixel clock with 2-lane pane, and the desired DSI clock divider
> >   is 12 with the output parent clock rate of 330MHz.
> > - 147MHz pixel clock with 4-lane panel, and the desired DSI clock divider
> >   is 6 with the output parent clock rate of 882MHz.
> >
> > BSP trying to use this format/lane to compute dsi divider that in-turn
> > using pll-mipi set_rate but TCON0_DCLK_REG keep constant 4.
>
> Feel free to reply to
> http://lists.infradead.org/pipermail/linux-arm-kernel/2019-February/629596.html

Yes, I have replied at that time itself, please check.

http://lists.infradead.org/pipermail/linux-arm-kernel/2019-February/629673.html

Here I have taken the pixel clock to 30Mhz for example in Bananapi
panel, and the above gist the pixel is 148Mhz from another panel.