[PATCHv2] omapdrm: hdmi4_cec: Fix CEC clock handling for PM

[Hans Verkuil]

On 3/26/19 4:14 PM, Tony Lindgren wrote:
> If CONFIG_OMAP4_DSS_HDMI_CEC is enabled in .config, deeper SoC idle
> states are blocked because the CEC clock gets always enabled on init.
> 
> Let's fix the issue by moving the CEC clock handling to happen later in
> hdmi_cec_adap_enable() as suggested by Hans Verkuil <hverkuil at xs4all.nl>.
> This way the CEC clock gets only enabled when needed. This can be tested
> by doing cec-ctl --playback to enable the CEC, and doing cec-ctl --clear
> to disable it.
> 
> Let's also fix the typo for "divider" in the comments while at it.
> 
> Fixes: 8d7f934df8d8 ("omapdrm: hdmi4_cec: add OMAP4 HDMI CEC support")
> Suggested-by: Hans Verkuil <hverkuil at xs4all.nl>
> Cc: Hans Verkuil <hverkuil at xs4all.nl>
> Cc: Jyri Sarha <jsarha at ti.com>
> Cc: Laurent Pinchart <laurent.pinchart at ideasonboard.com>
> Signed-off-by: Tony Lindgren <tony at atomide.com>

Reviewed-by: Hans Verkuil <hverkuil-cisco at xs4all.nl>

Thank you!

Regards,

	Hans

> ---
> 
> Changes since v1:
> 
> - Move clock enable to happen after the whole disable section rather than
>   add a pointless test for enable as noted by Hans
> 
> - Move clock enable to happen after hdmi4_core_enable() as otherwise doing
>   cec-ctl --playback with no HDMI cable connected will cause imprecise
>   external abort as HDMI core is idled
> 
> - Disable CEC device on possible errors
> 
> ---
>  drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c | 26 ++++++++++++++++++-------
>  1 file changed, 19 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c b/drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c
> --- a/drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c
> +++ b/drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c
> @@ -175,6 +175,7 @@ static int hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
>  		REG_FLD_MOD(core->base, HDMI_CORE_SYS_INTR_UNMASK4, 0, 3, 3);
>  		hdmi_wp_clear_irqenable(core->wp, HDMI_IRQ_CORE);
>  		hdmi_wp_set_irqstatus(core->wp, HDMI_IRQ_CORE);
> +		REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0, 5, 0);
>  		hdmi4_core_disable(core);
>  		return 0;
>  	}
> @@ -182,16 +183,24 @@ static int hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
>  	if (err)
>  		return err;
>  
> +	/*
> +	 * Initialize CEC clock divider: CEC needs 2MHz clock hence
> +	 * set the divider to 24 to get 48/24=2MHz clock
> +	 */
> +	REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0x18, 5, 0);
> +
>  	/* Clear TX FIFO */
>  	if (!hdmi_cec_clear_tx_fifo(adap)) {
>  		pr_err("cec-%s: could not clear TX FIFO\n", adap->name);
> -		return -EIO;
> +		err = -EIO;
> +		goto err_disable_clk;
>  	}
>  
>  	/* Clear RX FIFO */
>  	if (!hdmi_cec_clear_rx_fifo(adap)) {
>  		pr_err("cec-%s: could not clear RX FIFO\n", adap->name);
> -		return -EIO;
> +		err = -EIO;
> +		goto err_disable_clk;
>  	}
>  
>  	/* Clear CEC interrupts */
> @@ -236,6 +245,12 @@ static int hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
>  		hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_1, temp);
>  	}
>  	return 0;
> +
> +err_disable_clk:
> +	REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0, 5, 0);
> +	hdmi4_core_disable(core);
> +
> +	return err;
>  }
>  
>  static int hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
> @@ -333,11 +348,8 @@ int hdmi4_cec_init(struct platform_device *pdev, struct hdmi_core_data *core,
>  		return ret;
>  	core->wp = wp;
>  
> -	/*
> -	 * Initialize CEC clock divider: CEC needs 2MHz clock hence
> -	 * set the devider to 24 to get 48/24=2MHz clock
> -	 */
> -	REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0x18, 5, 0);
> +	/* Disable clock initially, hdmi_cec_adap_enable() manages it */
> +	REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0, 5, 0);
>  
>  	ret = cec_register_adapter(core->adap, &pdev->dev);
>  	if (ret < 0) {
>