[PATCH] drm/bridge: fix anx6345 compilation for v5.5

[Daniel Vetter]

On Tue, Nov 12, 2019 at 6:59 PM Torsten Duwe <duwe at lst.de> wrote:
>
>
> The anx6345 driver originally was copied from anx78xx.c, which has meanwhile
> seen a few changes. In particular, the removal of drm_dp_link helpers and the
> discontinuation to include drm_bridge.h from drm_crtc.h breaks compilation
> in linux-5.5. Apply equivalents of these changes to anx6345.c.
>
> Signed-off-by: Torsten Duwe <duwe at suse.de>

Wait ... Maxime pushed this and it never compiled? What's going on here?
-Daniel

>
> ---
>
> The commits in question are ff1e8fb68ea06 and ee68c743f8d07, but I guess the
> next rebase will change these. next-20191112 plus the anx6345-v5a series plus
> this patch compile cleanly on arm64.
>
> --- a/drivers/gpu/drm/bridge/analogix/analogix-anx6345.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix-anx6345.c
> @@ -19,6 +19,7 @@
>  #include <linux/types.h>
>
>  #include <drm/drm_atomic_helper.h>
> +#include <drm/drm_bridge.h>
>  #include <drm/drm_crtc.h>
>  #include <drm/drm_crtc_helper.h>
>  #include <drm/drm_dp_helper.h>
> @@ -49,7 +50,6 @@ struct anx6345 {
>         struct i2c_client *client;
>         struct edid *edid;
>         struct drm_connector connector;
> -       struct drm_dp_link link;
>         struct drm_panel *panel;
>         struct regulator *dvdd12;
>         struct regulator *dvdd25;
> @@ -96,7 +96,7 @@ static ssize_t anx6345_aux_transfer(stru
>  static int anx6345_dp_link_training(struct anx6345 *anx6345)
>  {
>         unsigned int value;
> -       u8 dp_bw;
> +       u8 dp_bw, dpcd[2];
>         int err;
>
>         err = anx6345_clear_bits(anx6345->map[I2C_IDX_TXCOM],
> @@ -144,18 +143,34 @@ static int anx6345_dp_link_training(stru
>         if (err)
>                 return err;
>
> -       /* Check link capabilities */
> -       err = drm_dp_link_probe(&anx6345->aux, &anx6345->link);
> -       if (err < 0) {
> -               DRM_ERROR("Failed to probe link capabilities: %d\n", err);
> -               return err;
> -       }
> +       /*
> +        * Power up the sink (DP_SET_POWER register is only available on DPCD
> +        * v1.1 and later).
> +        */
> +       if (anx6345->dpcd[DP_DPCD_REV] >= 0x11) {
> +               err = drm_dp_dpcd_readb(&anx6345->aux, DP_SET_POWER, &dpcd[0]);
> +               if (err < 0) {
> +                       DRM_ERROR("Failed to read DP_SET_POWER register: %d\n",
> +                                 err);
> +                       return err;
> +               }
> +
> +               dpcd[0] &= ~DP_SET_POWER_MASK;
> +               dpcd[0] |= DP_SET_POWER_D0;
> +
> +               err = drm_dp_dpcd_writeb(&anx6345->aux, DP_SET_POWER, dpcd[0]);
> +               if (err < 0) {
> +                       DRM_ERROR("Failed to power up DisplayPort link: %d\n",
> +                                 err);
> +                       return err;
> +               }
>
> -       /* Power up the sink */
> -       err = drm_dp_link_power_up(&anx6345->aux, &anx6345->link);
> -       if (err < 0) {
> -               DRM_ERROR("Failed to power up DisplayPort link: %d\n", err);
> -               return err;
> +               /*
> +                * According to the DP 1.1 specification, a "Sink Device must
> +                * exit the power saving state within 1 ms" (Section 2.5.3.1,
> +                * Table 5-52, "Sink Control Field" (register 0x600).
> +                */
> +               usleep_range(1000, 2000);
>         }
>
>         /* Possibly enable downspread on the sink */
> @@ -194,20 +209,28 @@ static int anx6345_dp_link_training(stru
>         if (err)
>                 return err;
>
> -       value = drm_dp_link_rate_to_bw_code(anx6345->link.rate);
> +       dpcd[0] = drm_dp_max_link_rate(anx6345->dpcd);
> +       dpcd[0] = drm_dp_link_rate_to_bw_code(dpcd[0]);
>         err = regmap_write(anx6345->map[I2C_IDX_DPTX],
> -                          SP_DP_MAIN_LINK_BW_SET_REG, value);
> +                          SP_DP_MAIN_LINK_BW_SET_REG, dpcd[0]);
>         if (err)
>                 return err;
>
> +       dpcd[1] = drm_dp_max_lane_count(anx6345->dpcd);
> +
>         err = regmap_write(anx6345->map[I2C_IDX_DPTX],
> -                          SP_DP_LANE_COUNT_SET_REG, anx6345->link.num_lanes);
> +                          SP_DP_LANE_COUNT_SET_REG, dpcd[1]);
>         if (err)
>                 return err;
>
> -       err = drm_dp_link_configure(&anx6345->aux, &anx6345->link);
> +       if (drm_dp_enhanced_frame_cap(anx6345->dpcd))
> +               dpcd[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
> +
> +       err = drm_dp_dpcd_write(&anx6345->aux, DP_LINK_BW_SET, dpcd,
> +                               sizeof(dpcd));
> +
>         if (err < 0) {
> -               DRM_ERROR("Failed to configure DisplayPort link: %d\n", err);
> +               DRM_ERROR("Failed to configure link: %d\n", err);
>                 return err;
>         }
>


-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch