[PATCH 7/7] drm/omap: hdmi5: automatically choose limited/full range output
Laurent Pinchart
laurent.pinchart at ideasonboard.com
Tue Sep 3 15:38:59 UTC 2019
Hi Tomi,
Thank you for the patch.
On Mon, Sep 02, 2019 at 03:53:59PM +0300, Tomi Valkeinen wrote:
> Currently the HDMI driver uses always limited range RGB output. This
> patch improves the behavior by using limited range only if the output is
> identified as a HDMI display, and VIC > 1.
>
> Signed-off-by: Tomi Valkeinen <tomi.valkeinen at ti.com>
Acked-by: Laurent Pinchart <laurent.pinchart at ideasonboard.com>
> ---
> drivers/gpu/drm/omapdrm/dss/hdmi5_core.c | 121 ++++++++++++-----------
> 1 file changed, 65 insertions(+), 56 deletions(-)
>
> diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c b/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c
> index 4c588ec7634a..96f5cd17768c 100644
> --- a/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c
> +++ b/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c
> @@ -23,18 +23,6 @@
>
> #include "hdmi5_core.h"
>
> -/* only 24 bit color depth used for now */
> -static const struct csc_table csc_table_deepcolor[] = {
> - /* HDMI_DEEP_COLOR_24BIT */
> - [0] = { 7036, 0, 0, 32, 0, 7036, 0, 32, 0, 0, 7036, 32, },
> - /* HDMI_DEEP_COLOR_30BIT */
> - [1] = { 7015, 0, 0, 128, 0, 7015, 0, 128, 0, 0, 7015, 128, },
> - /* HDMI_DEEP_COLOR_36BIT */
> - [2] = { 7010, 0, 0, 512, 0, 7010, 0, 512, 0, 0, 7010, 512, },
> - /* FULL RANGE */
> - [3] = { 8192, 0, 0, 0, 0, 8192, 0, 0, 0, 0, 8192, 0, },
> -};
> -
> static void hdmi_core_ddc_init(struct hdmi_core_data *core)
> {
> void __iomem *base = core->base;
> @@ -397,14 +385,6 @@ static void hdmi_core_config_video_packetizer(struct hdmi_core_data *core)
> REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 0 : 2, 1, 0);
> }
>
> -static void hdmi_core_config_csc(struct hdmi_core_data *core)
> -{
> - int clr_depth = 0; /* 24 bit color depth */
> -
> - /* CSC_COLORDEPTH */
> - REG_FLD_MOD(core->base, HDMI_CORE_CSC_SCALE, clr_depth, 7, 4);
> -}
> -
> static void hdmi_core_config_video_sampler(struct hdmi_core_data *core)
> {
> int video_mapping = 1; /* for 24 bit color depth */
> @@ -469,47 +449,67 @@ static void hdmi_core_write_avi_infoframe(struct hdmi_core_data *core,
> REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, pr, 3, 0);
> }
>
> -static void hdmi_core_csc_config(struct hdmi_core_data *core,
> - struct csc_table csc_coeff)
> +static void hdmi_core_write_csc(struct hdmi_core_data *core,
> + const struct csc_table *csc_coeff)
> {
> void __iomem *base = core->base;
>
> - REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_MSB, csc_coeff.a1 >> 8 , 6, 0);
> - REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_LSB, csc_coeff.a1, 7, 0);
> - REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_MSB, csc_coeff.a2 >> 8, 6, 0);
> - REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_LSB, csc_coeff.a2, 7, 0);
> - REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_MSB, csc_coeff.a3 >> 8, 6, 0);
> - REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_LSB, csc_coeff.a3, 7, 0);
> - REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_MSB, csc_coeff.a4 >> 8, 6, 0);
> - REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_LSB, csc_coeff.a4, 7, 0);
> - REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_MSB, csc_coeff.b1 >> 8, 6, 0);
> - REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_LSB, csc_coeff.b1, 7, 0);
> - REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_MSB, csc_coeff.b2 >> 8, 6, 0);
> - REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_LSB, csc_coeff.b2, 7, 0);
> - REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_MSB, csc_coeff.b3 >> 8, 6, 0);
> - REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_LSB, csc_coeff.b3, 7, 0);
> - REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_MSB, csc_coeff.b4 >> 8, 6, 0);
> - REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_LSB, csc_coeff.b4, 7, 0);
> - REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_MSB, csc_coeff.c1 >> 8, 6, 0);
> - REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_LSB, csc_coeff.c1, 7, 0);
> - REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_MSB, csc_coeff.c2 >> 8, 6, 0);
> - REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_LSB, csc_coeff.c2, 7, 0);
> - REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_MSB, csc_coeff.c3 >> 8, 6, 0);
> - REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_LSB, csc_coeff.c3, 7, 0);
> - REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_MSB, csc_coeff.c4 >> 8, 6, 0);
> - REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_LSB, csc_coeff.c4, 7, 0);
> -
> + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_MSB, csc_coeff->a1 >> 8, 6, 0);
> + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_LSB, csc_coeff->a1, 7, 0);
> + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_MSB, csc_coeff->a2 >> 8, 6, 0);
> + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_LSB, csc_coeff->a2, 7, 0);
> + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_MSB, csc_coeff->a3 >> 8, 6, 0);
> + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_LSB, csc_coeff->a3, 7, 0);
> + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_MSB, csc_coeff->a4 >> 8, 6, 0);
> + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_LSB, csc_coeff->a4, 7, 0);
> + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_MSB, csc_coeff->b1 >> 8, 6, 0);
> + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_LSB, csc_coeff->b1, 7, 0);
> + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_MSB, csc_coeff->b2 >> 8, 6, 0);
> + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_LSB, csc_coeff->b2, 7, 0);
> + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_MSB, csc_coeff->b3 >> 8, 6, 0);
> + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_LSB, csc_coeff->b3, 7, 0);
> + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_MSB, csc_coeff->b4 >> 8, 6, 0);
> + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_LSB, csc_coeff->b4, 7, 0);
> + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_MSB, csc_coeff->c1 >> 8, 6, 0);
> + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_LSB, csc_coeff->c1, 7, 0);
> + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_MSB, csc_coeff->c2 >> 8, 6, 0);
> + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_LSB, csc_coeff->c2, 7, 0);
> + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_MSB, csc_coeff->c3 >> 8, 6, 0);
> + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_LSB, csc_coeff->c3, 7, 0);
> + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_MSB, csc_coeff->c4 >> 8, 6, 0);
> + REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_LSB, csc_coeff->c4, 7, 0);
> +
> + /* enable CSC */
> REG_FLD_MOD(base, HDMI_CORE_MC_FLOWCTRL, 0x1, 0, 0);
> }
>
> -static void hdmi_core_configure_range(struct hdmi_core_data *core)
> +static void hdmi_core_configure_range(struct hdmi_core_data *core,
> + enum hdmi_quantization_range range)
> {
> - struct csc_table csc_coeff = { 0 };
> + static const struct csc_table csc_limited_range = {
> + 7036, 0, 0, 32, 0, 7036, 0, 32, 0, 0, 7036, 32
> + };
> + static const struct csc_table csc_full_range = {
> + 8192, 0, 0, 0, 0, 8192, 0, 0, 0, 0, 8192, 0
> + };
> + const struct csc_table *csc_coeff;
> +
> + /* CSC_COLORDEPTH = 24 bits*/
> + REG_FLD_MOD(core->base, HDMI_CORE_CSC_SCALE, 0, 7, 4);
> +
> + switch (range) {
> + case HDMI_QUANTIZATION_RANGE_FULL:
> + csc_coeff = &csc_full_range;
> + break;
>
> - /* support limited range with 24 bit color depth for now */
> - csc_coeff = csc_table_deepcolor[0];
> + case HDMI_QUANTIZATION_RANGE_DEFAULT:
> + case HDMI_QUANTIZATION_RANGE_LIMITED:
> + default:
> + csc_coeff = &csc_limited_range;
> + break;
> + }
>
> - hdmi_core_csc_config(core, csc_coeff);
> + hdmi_core_write_csc(core, csc_coeff);
> }
>
> static void hdmi_core_enable_video_path(struct hdmi_core_data *core)
> @@ -600,9 +600,20 @@ void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
> struct videomode vm;
> struct hdmi_video_format video_format;
> struct hdmi_core_vid_config v_core_cfg;
> + enum hdmi_quantization_range range;
>
> hdmi_core_mask_interrupts(core);
>
> + if (cfg->hdmi_dvi_mode == HDMI_HDMI) {
> + char vic = cfg->infoframe.video_code;
> +
> + /* All CEA modes other than VIC 1 use limited quantization range. */
> + range = vic > 1 ? HDMI_QUANTIZATION_RANGE_LIMITED :
> + HDMI_QUANTIZATION_RANGE_FULL;
> + } else {
> + range = HDMI_QUANTIZATION_RANGE_FULL;
> + }
> +
> hdmi_core_init(&v_core_cfg, cfg);
>
> hdmi_wp_init_vid_fmt_timings(&video_format, &vm, cfg);
> @@ -616,9 +627,8 @@ void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
>
> hdmi_wp_video_config_interface(wp, &vm);
>
> - /* support limited range with 24 bit color depth for now */
> - hdmi_core_configure_range(core);
> - cfg->infoframe.quantization_range = HDMI_QUANTIZATION_RANGE_LIMITED;
> + hdmi_core_configure_range(core, range);
> + cfg->infoframe.quantization_range = range;
>
> /*
> * configure core video part, set software reset in the core
> @@ -628,7 +638,6 @@ void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
> hdmi_core_video_config(core, &v_core_cfg);
>
> hdmi_core_config_video_packetizer(core);
> - hdmi_core_config_csc(core);
> hdmi_core_config_video_sampler(core);
>
> if (cfg->hdmi_dvi_mode == HDMI_HDMI)
--
Regards,
Laurent Pinchart
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