[PATCH v2] drm/mcde: Some fixes to handling video mode
linus.walleij at linaro.org
Thu Sep 5 12:16:59 UTC 2019
On Tue, Sep 3, 2019 at 4:38 PM Stephan Gerhold <stephan at gerhold.net> wrote:
> On Tue, Sep 03, 2019 at 11:15:12AM +0200, Linus Walleij wrote:
> > /*
> > * This is the time to perform LP->HS on D-PHY
> > * FIXME: nowhere to get this from: DT property on the DSI?
> > + * values like 48 and 72 seen in the vendor code.
> > */
> > - val |= 0 << DSI_VID_DPHY_TIME_REG_WAKEUP_TIME_SHIFT;
> > + val |= 48 << DSI_VID_DPHY_TIME_REG_WAKEUP_TIME_SHIFT;
> > writel(val, d->regs + DSI_VID_DPHY_TIME);
> I just want to note that the Samsung S3 Mini (golden) seems to use 88
> here. I suppose we will need to see how important this property is,
> or if panels can also work with a slightly wrong value.
Yeah maybe we should just figure out what to do about this.
This is the wakeup time, in clock cycles, for a LP->HS
transition on the D-PHY.
The panel driver kind of knows knows this timing, so I
guess we should add a field to struct mipi_dsi_device
such as unsigned int lp_to_hs_wakep, but it needs to
come from the device tree since per the manual this
value is system dependent:
"reg_wakeup_time must be shorter than line duration and
depends on the D-PHY cell plus some pipelines delays inserted
by the DSI link. This value strongly depends on the PLL
programming and as it is a mix of analog and digital timing, it
is practically impossible to provide a general formula. By the
way, it has to be characterized at system level (validation
> > - writel(blkeol_pck, d->regs + DSI_VID_VCA_SETTING2);
> > + writel((blkeol_pck & DSI_VID_VCA_SETTING2_EXACT_BURST_LIMIT_MASK)
> > + << DSI_VID_VCA_SETTING2_EXACT_BURST_LIMIT_SHIFT,
> > + d->regs + DSI_VID_VCA_SETTING2);
> It does not make a difference in this case because SHIFT = 0,
> but shouldn't you normally shift before applying the mask?
> Otherwise, you would wipe out the lower bits before you shift them.
OK you're right, I fix it up and resend.
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