[PATCH 6/6] drm/nouveau: Program aperture field where necessary

[Thierry Reding]

From: Thierry Reding <treding at nvidia.com>

Some registers and instance block entries need the aperture to be
programmed correctly. This is important on recent Tegra GPUs where
the GPU actually checks the value of this field and faults if an
invalid aperture is programmed.

For example GV11B no longer supports VRAM and all memory is already
allocated from system (coherent or non-coherent), so make sure to
also program the right aperture.

Signed-off-by: Thierry Reding <treding at nvidia.com>
---
 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c | 7 +++++--
 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c | 5 +++--
 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c       | 7 ++++++-
 drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c        | 3 ++-
 4 files changed, 16 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c
index 728a1edbf98c..843ebb41dbc6 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c
@@ -201,6 +201,7 @@ gk104_fifo_gpfifo_fini(struct nvkm_fifo_chan *base)
 void
 gk104_fifo_gpfifo_init(struct nvkm_fifo_chan *base)
 {
+	u32 aperture = nvkm_memory_aperture(base->inst->memory) << 28;
 	struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
 	struct gk104_fifo *fifo = chan->fifo;
 	struct nvkm_device *device = fifo->base.engine.subdev.device;
@@ -208,7 +209,7 @@ gk104_fifo_gpfifo_init(struct nvkm_fifo_chan *base)
 	u32 coff = chan->base.chid * 8;
 
 	nvkm_mask(device, 0x800004 + coff, 0x000f0000, chan->runl << 16);
-	nvkm_wr32(device, 0x800000 + coff, 0x80000000 | addr);
+	nvkm_wr32(device, 0x800000 + coff, 0x80000000 | aperture | addr);
 
 	if (list_empty(&chan->head) && !chan->killed) {
 		gk104_fifo_runlist_insert(fifo, chan);
@@ -250,6 +251,7 @@ gk104_fifo_gpfifo_new_(struct gk104_fifo *fifo, u64 *runlists, u16 *chid,
 	unsigned long engm;
 	u64 subdevs = 0;
 	u64 usermem;
+	u32 target;
 
 	if (!vmm || runlist < 0 || runlist >= fifo->runlist_nr)
 		return -EINVAL;
@@ -303,10 +305,11 @@ gk104_fifo_gpfifo_new_(struct gk104_fifo *fifo, u64 *runlists, u16 *chid,
 		nvkm_wo32(fifo->user.mem, usermem + i, 0x00000000);
 	nvkm_done(fifo->user.mem);
 	usermem = nvkm_memory_addr(fifo->user.mem) + usermem;
+	target = nvkm_memory_aperture(fifo->user.mem);
 
 	/* RAMFC */
 	nvkm_kmap(chan->base.inst);
-	nvkm_wo32(chan->base.inst, 0x08, lower_32_bits(usermem));
+	nvkm_wo32(chan->base.inst, 0x08, lower_32_bits(usermem) | target);
 	nvkm_wo32(chan->base.inst, 0x0c, upper_32_bits(usermem));
 	nvkm_wo32(chan->base.inst, 0x10, 0x0000face);
 	nvkm_wo32(chan->base.inst, 0x30, 0xfffff902);
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c
index a7462cf59d65..97d084ffcfd5 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c
@@ -132,7 +132,7 @@ gv100_fifo_gpfifo_new_(const struct nvkm_fifo_chan_func *func,
 	unsigned long engm;
 	u64 subdevs = 0;
 	u64 usermem, mthd;
-	u32 size;
+	u32 size, target;
 
 	if (!vmm || runlist < 0 || runlist >= fifo->runlist_nr)
 		return -EINVAL;
@@ -183,6 +183,7 @@ gv100_fifo_gpfifo_new_(const struct nvkm_fifo_chan_func *func,
 		nvkm_wo32(fifo->user.mem, usermem + i, 0x00000000);
 	nvkm_done(fifo->user.mem);
 	usermem = nvkm_memory_addr(fifo->user.mem) + usermem;
+	target = nvkm_memory_target(fifo->user.mem);
 
 	/* Allocate fault method buffer (magics come from nvgpu). */
 	size = nvkm_rd32(device, 0x104028); /* NV_PCE_PCE_MAP */
@@ -200,7 +201,7 @@ gv100_fifo_gpfifo_new_(const struct nvkm_fifo_chan_func *func,
 
 	/* RAMFC */
 	nvkm_kmap(chan->base.inst);
-	nvkm_wo32(chan->base.inst, 0x008, lower_32_bits(usermem));
+	nvkm_wo32(chan->base.inst, 0x008, lower_32_bits(usermem) | target);
 	nvkm_wo32(chan->base.inst, 0x00c, upper_32_bits(usermem));
 	nvkm_wo32(chan->base.inst, 0x010, 0x0000face);
 	nvkm_wo32(chan->base.inst, 0x030, 0x7ffff902);
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c
index 6ee1bb32a071..449f669f43b0 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c
@@ -32,11 +32,16 @@ void
 gv100_fifo_runlist_chan(struct gk104_fifo_chan *chan,
 			struct nvkm_memory *memory, u32 offset)
 {
+	struct nvkm_memory *instmem = chan->base.inst->memory;
 	struct nvkm_memory *usermem = chan->fifo->user.mem;
 	const u64 user = nvkm_memory_addr(usermem) + (chan->base.chid * 0x200);
 	const u64 inst = chan->base.inst->addr;
+	u64 target;
 
-	nvkm_wo32(memory, offset + 0x0, lower_32_bits(user));
+	target = (u64)nvkm_memory_aperture(usermem) << 6 |
+		 (u64)nvkm_memory_aperture(instmem) << 4;
+
+	nvkm_wo32(memory, offset + 0x0, lower_32_bits(user) | target);
 	nvkm_wo32(memory, offset + 0x4, upper_32_bits(user));
 	nvkm_wo32(memory, offset + 0x8, lower_32_bits(inst) | chan->base.chid);
 	nvkm_wo32(memory, offset + 0xc, upper_32_bits(inst));
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c
index a3dcb09a40ee..5b193a7bf5de 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c
@@ -54,7 +54,8 @@ gf100_bar_bar1_init(struct nvkm_bar *base)
 	struct nvkm_device *device = base->subdev.device;
 	struct gf100_bar *bar = gf100_bar(base);
 	const u32 addr = nvkm_memory_addr(bar->bar[1].inst) >> 12;
-	nvkm_wr32(device, 0x001704, 0x80000000 | addr);
+	u32 target = nvkm_memory_aperture(bar->bar[1].inst) << 28;
+	nvkm_wr32(device, 0x001704, 0x80000000 | target | addr);
 }
 
 struct nvkm_vmm *
-- 
2.23.0