[PATCH] drm/omap: Migrate minimum FCK/PCK ratio from Kconfig to dts

Tomi Valkeinen tomi.valkeinen at ti.com
Fri Sep 27 13:47:46 UTC 2019

On 27/09/2019 15:33, Adam Ford wrote:

>> It looks like a bug in omap clock handling.
>> DSS uses dss1_alwon_fck_3430es2 as fclk. dss1_alwon_fck_3430es2 comes
>> from dpll4_ck, and there's a divider after the PLL, dpll4_m4_ck.
>> When the DSS driver sets dss1_alwon_fck_3430es2 rate to 27000000 or
>> 27870967, which can be created with m4 dividers 32 and 31, it looks like
>> the divider goes to bypass, or to a very small value. DSS gets a very
>> high clock rate and breaks down.
> Is there anything I can do to help troubleshoot this?  I could insert
> a hack that checks if we're omap3 and if so make the divider equal to
> 4, but that seems like just a hack.
> I can run more tests or insert code somewhere if you want.

I think it's up to someone who's knowledgeable in omap clock framework. 
I'm kind of hoping that Tero or Tony would be willing to debug =). I can 
try to find time to debug the omap clk framework, but I'll be going on 
blindly there.


Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

More information about the dri-devel mailing list