[PATCH] drm/omap: Migrate minimum FCK/PCK ratio from Kconfig to dts
tomi.valkeinen at ti.com
Mon Sep 30 14:20:22 UTC 2019
On 30/09/2019 17:12, Adam Ford wrote:
>> I don't know the implications, so if the people from TI say stick with
>> 16, I'm fine with that, but at least there is some evidence that it
>> can be higher than 16, but lower than 32.
> Sorry for all the spam, but I moved both of them to 31 from 32, and it
> also seems to work successfully at 31.
> [ 26.923004] DSS: set fck to 36000000
> [ 26.923034] DISPC: lck = 36000000 (1)
> [ 26.923034] DISPC: pck = 9000000 (4)
> [ 26.925048] DISPC: channel 0 xres 480 yres 272
> [ 26.925048] DISPC: pck 9000000
> [ 26.925048] DISPC: hsync_len 42 hfp 3 hbp 2 vsw 11 vfp 2 vbp 3
> [ 26.925079] DISPC: vsync_level 1 hsync_level 1 data_pclk_edge 1
> de_level 1 sync_pclk_edge -1
> [ 26.925079] DISPC: hsync 17077Hz, vsync 59Hz
> [ 27.384613] DISPC: dispc_runtime_put
> Is it possible to use 31?
Let's see what Tero says, but yeah, something is odd here. I expected
the max divider to be 16 with Tero's patch, but I don't see it having
that effect. I can get the div to 31.
You can see this from the clock register 0x48004e40 (CM_CLKSEL_DSS). The
lowest bits are the divider, 5 to 0. The TRM says max div is 32.
Tero said for him the dividers > 16 didn't "stick" to the register. I'm
now wondering if he has an old beagleboard with OMAP34xx, which has max
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