[PATCH v7 08/12] arm: dts: s5pv210: Add node for SGX 540

[Krzysztof Kozlowski]

On Sun, Apr 26, 2020 at 07:57:12AM -0700, Jonathan Bakker wrote:
> Hi Paul,
> 
> On 2020-04-26 5:56 a.m., Paul Cercueil wrote:
> > 
> > 
> > Le ven. 24 avril 2020 à 22:34, H. Nikolaus Schaller <hns at goldelico.com> a écrit :
> >> From: Jonathan Bakker <xc-racer2 at live.ca>
> >>
> >> All s5pv210 devices have a PowerVR SGX 540 (revision 120) attached.
> >>
> >> There is no external regulator for it so it can be enabled by default.
> >>
> >> Signed-off-by: Jonathan Bakker <xc-racer2 at live.ca>
> >> Signed-off-by: H. Nikolaus Schaller <hns at goldelico.com>
> >> ---
> >>  arch/arm/boot/dts/s5pv210.dtsi | 13 +++++++++++++
> >>  1 file changed, 13 insertions(+)
> >>
> >> diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi
> >> index 2ad642f51fd9..abbdda205c1b 100644
> >> --- a/arch/arm/boot/dts/s5pv210.dtsi
> >> +++ b/arch/arm/boot/dts/s5pv210.dtsi
> >> @@ -512,6 +512,19 @@ vic3: interrupt-controller at f2300000 {
> >>              #interrupt-cells = <1>;
> >>          };
> >>
> >> +        gpu: gpu at f3000000 {
> >> +            compatible = "samsung,s5pv210-sgx540-120";

This should not pass the bindings check because you missed last
compatibles.

> >> +            reg = <0xf3000000 0x10000>;
> >> +            interrupt-parent = <&vic2>;
> >> +            interrupts = <10>;
> >> +            clock-names = "core";
> >> +            clocks = <&clocks CLK_G3D>;
> >> +
> >> +            assigned-clocks = <&clocks MOUT_G3D>, <&clocks DOUT_G3D>;
> >> +            assigned-clock-rates = <0>, <66700000>;
> >> +            assigned-clock-parents = <&clocks MOUT_MPLL>;
> > 
> > What are these clocks for, and why are they reparented / reclocked?
> > 
> > Shouldn't they be passed to 'clocks' as well?
> > 
> > -Paul
> > 
> 
> The G3D clock system can have multiple parents, and for stable operation
> it's recommended to use the MPLL clock as the parent (which in turn
> is actually a mux as well).  MOUT_G3D is simply the mux for CLK_G3D
> (SGX core clock), DOUT_G3D is the divider.  DOUT_G3D could equally be CLK_G3D
> (and probably should be, for readability) as CLK_G3D is simply the gate and
> DOUT_G3D is the divider for it.

Good point, it should be CLK_G3D instead of DOUT.  Can you fix this as
well?

Best regards,
Krzysztof