[RESEND v7, PATCH 1/7] dt-bindings: mediatek: add rdma_fifo_size description for mt8183 display

[Chun-Kuang Hu]

Hi, Yongqiang:

Yongqiang Niu <yongqiang.niu at mediatek.com> 於 2020年8月8日 週六 上午11:04寫道：
>
> rdma fifo size may be different even in same SOC, add this
> property to the corresponding rdma
>
> Change-Id: I67635ec7f3f59cf4cbc7737285e5e28ff0ab71c9

Remove change-id.

> Signed-off-by: Yongqiang Niu <yongqiang.niu at mediatek.com>
> ---
>  .../devicetree/bindings/display/mediatek/mediatek,disp.txt | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> index b91e709..e6bbe32 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> @@ -66,6 +66,11 @@ Required properties (DMA function blocks):
>    argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
>    for details.
>
> +Optional properties (RDMA function blocks):
> +- mediatek,rdma_fifo_size: rdma fifo size may be different even in same SOC, add this
> +  property to the corresponding rdma
> +  the value is the Max value which defined in hardware data sheet.
> +
>  Examples:
>
>  mmsys: clock-controller at 14000000 {
> @@ -207,3 +212,12 @@ od at 14023000 {
>         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
>         clocks = <&mmsys CLK_MM_DISP_OD>;
>  };
> +
> +rdma1: rdma at 1400c000 {
> +       compatible = "mediatek,mt8183-disp-rdma";
> +       reg = <0 0x1400c000 0 0x1000>;
> +       interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
> +       power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> +       clocks = <&mmsys CLK_MM_DISP_RDMA1>;
> +       mediatek,rdma_fifo_size = <2048>;
> +};

I would like you to show rdma0 as well so that could prove two rdma
have different fifo size in the same SoC.

Regards,
Chun-Kuang.

> --
> 1.8.1.1.dirty
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