[PATCH v1 21/21] arm64: dts: mt8192: add display node
Rob Herring
robh+dt at kernel.org
Thu Aug 20 13:23:39 UTC 2020
On Thu, Aug 20, 2020 at 12:06 AM Yongqiang Niu
<yongqiang.niu at mediatek.com> wrote:
>
> add display node
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu at mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 126 +++++++++++++++++++++++++++++++
> 1 file changed, 126 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 931e1ca..d2a814d 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -17,6 +17,13 @@
> #address-cells = <2>;
> #size-cells = <2>;
>
> + aliases {
> + ovl0 = &ovl0;
> + ovl_2l0 = &ovl_2l0;
> + ovl_2l2 = &ovl_2l2;
> + rdma0 = &rdma0;
> + rdma4 = &rdma4;
No, please don't add a bunch of custom aliases that you probably don't need.
> + };
> clk26m: oscillator at 0 {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> @@ -449,6 +456,125 @@
> #clock-cells = <1>;
> };
>
> + mutex: mutex at 14001000 {
> + compatible = "mediatek,mt8192-disp-mutex";
> + reg = <0 0x14001000 0 0x1000>;
> + interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&mmsys CLK_MM_DISP_CONFIG>,
> + <&mmsys CLK_MM_26MHZ>,
> + <&mmsys CLK_MM_DISP_MUTEX0>;
> + };
> + ovl0: ovl at 14005000 {
> + compatible = "mediatek,mt8192-disp-ovl";
> + reg = <0 0x14005000 0 0x1000>;
> + interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&mmsys CLK_MM_DISP_OVL0>;
> + //iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
> + // <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
> + power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> + //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
> + };
> +
> + ovl_2l0: ovl at 14006000 {
> + compatible = "mediatek,mt8192-disp-ovl-2l";
> + reg = <0 0x14006000 0 0x1000>;
> + interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>;
> + power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> + //iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
> + // <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
> + //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
> + };
> +
> + rdma0: rdma at 14007000 {
> + compatible = "mediatek,mt8192-disp-rdma";
> + reg = <0 0x14007000 0 0x1000>;
> + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> + //iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
> + mediatek,rdma_fifo_size = <5>;
> + power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> + //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
> + };
> +
> + color0: color at 14009000 {
> + compatible = "mediatek,mt8192-disp-color",
> + "mediatek,mt8173-disp-color";
> + reg = <0 0x14009000 0 0x1000>;
> + interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
> + power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> + //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
> + };
> +
> + ccorr0: ccorr at 1400a000 {
> + compatible = "mediatek,mt8192-disp-ccorr";
> + reg = <0 0x1400a000 0 0x1000>;
> + interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
> + power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> + //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
> + };
> +
> + aal0: aal at 1400b000 {
> + compatible = "mediatek,mt8192-disp-aal";
> + reg = <0 0x1400b000 0 0x1000>;
> + interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
> + power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_AAL0>;
> + //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
> + };
> +
> + gamma0: gamma at 1400c000 {
> + compatible = "mediatek,mt8192-disp-gamma";
> + reg = <0 0x1400c000 0 0x1000>;
> + interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
> + power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
> + //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
> + };
> +
> + postmask0: postmask at 1400d000 {
> + compatible = "mediatek,mt8192-disp-postmask";
> + reg = <0 0x1400d000 0 0x1000>;
> + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
> + power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
> + //iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>;
> + //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
> + };
> +
> + dither0: dither at 1400e000 {
> + compatible = "mediatek,mt8192-disp-dither";
> + reg = <0 0x1400e000 0 0x1000>;
> + interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
> + power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> + //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
> + };
> +
> + ovl_2l2: ovl at 14014000 {
> + compatible = "mediatek,mt8192-disp-ovl-2l";
> + reg = <0 0x14014000 0 0x1000>;
> + interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>;
> + power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
> + //iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
> + // <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
> + //mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
> + };
> +
> + rdma4: rdma at 14015000 {
> + compatible = "mediatek,mt8192-disp-rdma";
> + reg = <0 0x14015000 0 0x1000>;
> + interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>;
> + power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_RDMA4>;
> + //iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
> + mediatek,rdma_fifo_size = <2>;
> + //mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
> + };
> +
> imgsys: imgsys at 15020000 {
> compatible = "mediatek,mt8192-imgsys", "syscon";
> reg = <0 0x15020000 0 0x1000>;
> --
> 1.8.1.1.dirty
More information about the dri-devel
mailing list