[RFT 3/4] ARM: dts: exynos: Move CMU assigned ISP clocks to buses in Exynos3250

[Marek Szyprowski]

Hi Krzysztof,

On 29.08.2020 19:25, Krzysztof Kozlowski wrote:
> Commit 52005dece527 ("ARM: dts: Add assigned clock parents to CMU node
> for exynos3250") added assigned clocks under Clock Management Unit to
> fix hangs when accessing ISP registers.
>
> This is not the place for it as CMU does not have a required "clocks"
> property:
>
>    arch/arm/boot/dts/exynos3250-artik5-eval.dt.yaml: clock-controller at 10030000: 'clocks' is a dependency of 'assigned-clocks'
>
> Signed-off-by: Krzysztof Kozlowski <krzk at kernel.org>
>
> ---
>
> Not tested and I wonder whether actually correct. For example, what will
> happen if devfreq (exynos-bus) is not built in?
>
> Could someone verify it?

Sorry, but this patch is not correct. Those clocks has noting with 
bus-freq. The assigned clocks property should stay where it is. Maybe 
one need to fix the schemas for dts verification. Those clocks has to be 
set (and so generic clock framework does) according to the assigned 
clocks properties once the clock controller is instantiated.

The only alternative would be to add exynos-subcmu variant to properly 
link CMU with the ISP power domain, but assuming that there is no Exynos 
3250 ISP driver in mainline (and probably never will be), it is safe to 
keep those clocks sourced from 24MHz crystal.


> ---
>   arch/arm/boot/dts/exynos3250.dtsi | 8 ++++----
>   1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
> index c67c70e46794..6d467022d929 100644
> --- a/arch/arm/boot/dts/exynos3250.dtsi
> +++ b/arch/arm/boot/dts/exynos3250.dtsi
> @@ -214,10 +214,6 @@
>   			compatible = "samsung,exynos3250-cmu";
>   			reg = <0x10030000 0x20000>;
>   			#clock-cells = <1>;
> -			assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>,
> -					  <&cmu CLK_MOUT_ACLK_266_SUB>;
> -			assigned-clock-parents = <&cmu CLK_FIN_PLL>,
> -						 <&cmu CLK_FIN_PLL>;
>   		};
>   
>   		cmu_dmc: clock-controller at 105c0000 {
> @@ -835,6 +831,8 @@
>   			compatible = "samsung,exynos-bus";
>   			clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
>   			clock-names = "bus";
> +			assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>;
> +			assigned-clock-parents = <&cmu CLK_FIN_PLL>;
>   			operating-points-v2 = <&bus_mcuisp_opp_table>;
>   			status = "disabled";
>   		};
> @@ -843,6 +841,8 @@
>   			compatible = "samsung,exynos-bus";
>   			clocks = <&cmu CLK_DIV_ACLK_266>;
>   			clock-names = "bus";
> +			assigned-clocks =  <&cmu CLK_MOUT_ACLK_266_SUB>;
> +			assigned-clock-parents = <&cmu CLK_FIN_PLL>;
>   			operating-points-v2 = <&bus_isp_opp_table>;
>   			status = "disabled";
>   		};

Best regards
-- 
Marek Szyprowski, PhD
Samsung R&D Institute Poland