[PATCH 3/8] drm/vmwgfx: Switch to a managed drm device
kernel test robot
lkp at intel.com
Wed Dec 2 00:46:15 UTC 2020
Hi Zack,
I love your patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on tegra-drm/drm/tegra/for-next linus/master v5.10-rc6]
[cannot apply to drm-exynos/exynos-drm-next drm-tip/drm-tip drm/drm-next next-20201201]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Zack-Rusin/drm-vmwgfx-add-Zack-Rusin-as-maintainer/20201202-043705
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-rhel (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0
reproduce (this is a W=1 build):
# https://github.com/0day-ci/linux/commit/29587b40449b0290424fbb9083dc47b1869ef7d5
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Zack-Rusin/drm-vmwgfx-add-Zack-Rusin-as-maintainer/20201202-043705
git checkout 29587b40449b0290424fbb9083dc47b1869ef7d5
# save the attached .config to linux build tree
make W=1 ARCH=x86_64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp at intel.com>
All errors (new ones prefixed by >>):
drivers/gpu/drm/vmwgfx/vmwgfx_drv.c: In function 'vmw_driver_load':
>> drivers/gpu/drm/vmwgfx/vmwgfx_drv.c:794:36: error: invalid type argument of '->' (have 'struct drm_device')
794 | dma_set_max_seg_size(dev_priv->drm->dev, min_t(unsigned int, U32_MAX & PAGE_MASK,
| ^~
>> drivers/gpu/drm/vmwgfx/vmwgfx_drv.c:866:6: error: 'dev' undeclared (first use in this function); did you mean 'cdev'?
866 | dev->anon_inode->i_mapping,
| ^~~
| cdev
drivers/gpu/drm/vmwgfx/vmwgfx_drv.c:866:6: note: each undeclared identifier is reported only once for each function it appears in
--
drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c: In function 'vmw_ttm_populate':
>> drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c:595:54: error: 'struct vmw_private' has no member named 'dev'; did you mean 'bdev'?
595 | ret = ttm_dma_populate(&vmw_tt->dma_ttm, dev_priv->dev->dev,
| ^~~
| bdev
drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c: In function 'vmw_ttm_unpopulate':
drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c:624:50: error: 'struct vmw_private' has no member named 'dev'; did you mean 'bdev'?
624 | ttm_dma_unpopulate(&vmw_tt->dma_ttm, dev_priv->dev->dev);
| ^~~
| bdev
vim +794 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
651
652 static int vmw_driver_load(struct vmw_private *dev_priv, unsigned long chipset)
653 {
654 int ret;
655 uint32_t svga_id;
656 enum vmw_res_type i;
657 bool refuse_dma = false;
658 char host_log[100] = {0};
659
660 pci_set_master(dev_priv->drm.pdev);
661
662 dev_priv->vmw_chipset = chipset;
663 dev_priv->last_read_seqno = (uint32_t) -100;
664 mutex_init(&dev_priv->cmdbuf_mutex);
665 mutex_init(&dev_priv->release_mutex);
666 mutex_init(&dev_priv->binding_mutex);
667 mutex_init(&dev_priv->global_kms_state_mutex);
668 ttm_lock_init(&dev_priv->reservation_sem);
669 spin_lock_init(&dev_priv->resource_lock);
670 spin_lock_init(&dev_priv->hw_lock);
671 spin_lock_init(&dev_priv->waiter_lock);
672 spin_lock_init(&dev_priv->cap_lock);
673 spin_lock_init(&dev_priv->svga_lock);
674 spin_lock_init(&dev_priv->cursor_lock);
675
676 for (i = vmw_res_context; i < vmw_res_max; ++i) {
677 idr_init(&dev_priv->res_idr[i]);
678 INIT_LIST_HEAD(&dev_priv->res_lru[i]);
679 }
680
681 init_waitqueue_head(&dev_priv->fence_queue);
682 init_waitqueue_head(&dev_priv->fifo_queue);
683 dev_priv->fence_queue_waiters = 0;
684 dev_priv->fifo_queue_waiters = 0;
685
686 dev_priv->used_memory_size = 0;
687
688 dev_priv->io_start = pci_resource_start(dev_priv->drm.pdev, 0);
689 dev_priv->vram_start = pci_resource_start(dev_priv->drm.pdev, 1);
690 dev_priv->mmio_start = pci_resource_start(dev_priv->drm.pdev, 2);
691
692 dev_priv->assume_16bpp = !!vmw_assume_16bpp;
693
694 dev_priv->enable_fb = enable_fbdev;
695
696 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
697 svga_id = vmw_read(dev_priv, SVGA_REG_ID);
698 if (svga_id != SVGA_ID_2) {
699 ret = -ENOSYS;
700 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id);
701 goto out_err0;
702 }
703
704 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
705
706 if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) {
707 dev_priv->capabilities2 = vmw_read(dev_priv, SVGA_REG_CAP2);
708 }
709
710
711 ret = vmw_dma_select_mode(dev_priv);
712 if (unlikely(ret != 0)) {
713 DRM_INFO("Restricting capabilities since DMA not available.\n");
714 refuse_dma = true;
715 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS)
716 DRM_INFO("Disabling 3D acceleration.\n");
717 }
718
719 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
720 dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
721 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
722 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
723
724 vmw_get_initial_size(dev_priv);
725
726 if (dev_priv->capabilities & SVGA_CAP_GMR2) {
727 dev_priv->max_gmr_ids =
728 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
729 dev_priv->max_gmr_pages =
730 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES);
731 dev_priv->memory_size =
732 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE);
733 dev_priv->memory_size -= dev_priv->vram_size;
734 } else {
735 /*
736 * An arbitrary limit of 512MiB on surface
737 * memory. But all HWV8 hardware supports GMR2.
738 */
739 dev_priv->memory_size = 512*1024*1024;
740 }
741 dev_priv->max_mob_pages = 0;
742 dev_priv->max_mob_size = 0;
743 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
744 uint64_t mem_size;
745
746 if (dev_priv->capabilities2 & SVGA_CAP2_GB_MEMSIZE_2)
747 mem_size = vmw_read(dev_priv,
748 SVGA_REG_GBOBJECT_MEM_SIZE_KB);
749 else
750 mem_size =
751 vmw_read(dev_priv,
752 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB);
753
754 /*
755 * Workaround for low memory 2D VMs to compensate for the
756 * allocation taken by fbdev
757 */
758 if (!(dev_priv->capabilities & SVGA_CAP_3D))
759 mem_size *= 3;
760
761 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE;
762 dev_priv->prim_bb_mem =
763 vmw_read(dev_priv,
764 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM);
765 dev_priv->max_mob_size =
766 vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE);
767 dev_priv->stdu_max_width =
768 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH);
769 dev_priv->stdu_max_height =
770 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT);
771
772 vmw_write(dev_priv, SVGA_REG_DEV_CAP,
773 SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH);
774 dev_priv->texture_max_width = vmw_read(dev_priv,
775 SVGA_REG_DEV_CAP);
776 vmw_write(dev_priv, SVGA_REG_DEV_CAP,
777 SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT);
778 dev_priv->texture_max_height = vmw_read(dev_priv,
779 SVGA_REG_DEV_CAP);
780 } else {
781 dev_priv->texture_max_width = 8192;
782 dev_priv->texture_max_height = 8192;
783 dev_priv->prim_bb_mem = dev_priv->vram_size;
784 }
785
786 vmw_print_capabilities(dev_priv->capabilities);
787 if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER)
788 vmw_print_capabilities2(dev_priv->capabilities2);
789
790 ret = vmw_dma_masks(dev_priv);
791 if (unlikely(ret != 0))
792 goto out_err0;
793
> 794 dma_set_max_seg_size(dev_priv->drm->dev, min_t(unsigned int, U32_MAX & PAGE_MASK,
795 SCATTERLIST_MAX_SEGMENT));
796
797 if (dev_priv->capabilities & SVGA_CAP_GMR2) {
798 DRM_INFO("Max GMR ids is %u\n",
799 (unsigned)dev_priv->max_gmr_ids);
800 DRM_INFO("Max number of GMR pages is %u\n",
801 (unsigned)dev_priv->max_gmr_pages);
802 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n",
803 (unsigned)dev_priv->memory_size / 1024);
804 }
805 DRM_INFO("Maximum display memory size is %u kiB\n",
806 dev_priv->prim_bb_mem / 1024);
807 DRM_INFO("VRAM at 0x%08x size is %u kiB\n",
808 dev_priv->vram_start, dev_priv->vram_size / 1024);
809 DRM_INFO("MMIO at 0x%08x size is %u kiB\n",
810 dev_priv->mmio_start, dev_priv->mmio_size / 1024);
811
812 dev_priv->mmio_virt = memremap(dev_priv->mmio_start,
813 dev_priv->mmio_size, MEMREMAP_WB);
814
815 if (unlikely(dev_priv->mmio_virt == NULL)) {
816 ret = -ENOMEM;
817 DRM_ERROR("Failed mapping MMIO.\n");
818 goto out_err0;
819 }
820
821 /* Need mmio memory to check for fifo pitchlock cap. */
822 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
823 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) &&
824 !vmw_fifo_have_pitchlock(dev_priv)) {
825 ret = -ENOSYS;
826 DRM_ERROR("Hardware has no pitchlock\n");
827 goto out_err4;
828 }
829
830 dev_priv->tdev = ttm_object_device_init(&ttm_mem_glob, 12,
831 &vmw_prime_dmabuf_ops);
832
833 if (unlikely(dev_priv->tdev == NULL)) {
834 DRM_ERROR("Unable to initialize TTM object management.\n");
835 ret = -ENOMEM;
836 goto out_err4;
837 }
838
839 dev_priv->drm.dev_private = dev_priv;
840
841 ret = pci_request_regions(dev_priv->drm.pdev, "vmwgfx probe");
842 if (ret) {
843 DRM_ERROR("Failed reserving PCI regions.\n");
844 goto out_no_device;
845 }
846
847 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
848 ret = vmw_irq_install(&dev_priv->drm, dev_priv->drm.pdev->irq);
849 if (ret != 0) {
850 DRM_ERROR("Failed installing irq: %d\n", ret);
851 goto out_no_irq;
852 }
853 }
854
855 dev_priv->fman = vmw_fence_manager_init(dev_priv);
856 if (unlikely(dev_priv->fman == NULL)) {
857 ret = -ENOMEM;
858 goto out_no_fman;
859 }
860
861 drm_vma_offset_manager_init(&dev_priv->vma_manager,
862 DRM_FILE_PAGE_OFFSET_START,
863 DRM_FILE_PAGE_OFFSET_SIZE);
864 ret = ttm_bo_device_init(&dev_priv->bdev,
865 &vmw_bo_driver,
> 866 dev->anon_inode->i_mapping,
867 &dev_priv->vma_manager,
868 false);
869 if (unlikely(ret != 0)) {
870 DRM_ERROR("Failed initializing TTM buffer object driver.\n");
871 goto out_no_bdev;
872 }
873
874 /*
875 * Enable VRAM, but initially don't use it until SVGA is enabled and
876 * unhidden.
877 */
878
879 ret = vmw_vram_manager_init(dev_priv);
880 if (unlikely(ret != 0)) {
881 DRM_ERROR("Failed initializing memory manager for VRAM.\n");
882 goto out_no_vram;
883 }
884
885 /*
886 * "Guest Memory Regions" is an aperture like feature with
887 * one slot per bo. There is an upper limit of the number of
888 * slots as well as the bo size.
889 */
890 dev_priv->has_gmr = true;
891 /* TODO: This is most likely not correct */
892 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) ||
893 refuse_dma ||
894 vmw_gmrid_man_init(dev_priv, VMW_PL_GMR) != 0) {
895 DRM_INFO("No GMR memory available. "
896 "Graphics memory resources are very limited.\n");
897 dev_priv->has_gmr = false;
898 }
899
900 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS && !refuse_dma) {
901 dev_priv->has_mob = true;
902
903 if (vmw_gmrid_man_init(dev_priv, VMW_PL_MOB) != 0) {
904 DRM_INFO("No MOB memory available. "
905 "3D will be disabled.\n");
906 dev_priv->has_mob = false;
907 }
908 }
909
910 if (dev_priv->has_mob && (dev_priv->capabilities & SVGA_CAP_DX)) {
911 spin_lock(&dev_priv->cap_lock);
912 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_DXCONTEXT);
913 if (vmw_read(dev_priv, SVGA_REG_DEV_CAP))
914 dev_priv->sm_type = VMW_SM_4;
915 spin_unlock(&dev_priv->cap_lock);
916 }
917
918 vmw_validation_mem_init_ttm(dev_priv, VMWGFX_VALIDATION_MEM_GRAN);
919
920 /* SVGA_CAP2_DX2 (DefineGBSurface_v3) is needed for SM4_1 support */
921 if (has_sm4_context(dev_priv) &&
922 (dev_priv->capabilities2 & SVGA_CAP2_DX2)) {
923 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_SM41);
924
925 if (vmw_read(dev_priv, SVGA_REG_DEV_CAP))
926 dev_priv->sm_type = VMW_SM_4_1;
927
928 if (has_sm4_1_context(dev_priv) &&
929 (dev_priv->capabilities2 & SVGA_CAP2_DX3)) {
930 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_SM5);
931 if (vmw_read(dev_priv, SVGA_REG_DEV_CAP))
932 dev_priv->sm_type = VMW_SM_5;
933 }
934 }
935
936 ret = vmw_kms_init(dev_priv);
937 if (unlikely(ret != 0))
938 goto out_no_kms;
939 vmw_overlay_init(dev_priv);
940
941 ret = vmw_request_device(dev_priv);
942 if (ret)
943 goto out_no_fifo;
944
945 DRM_INFO("Atomic: %s\n", (dev_priv->drm.driver->driver_features & DRIVER_ATOMIC)
946 ? "yes." : "no.");
947 if (dev_priv->sm_type == VMW_SM_5)
948 DRM_INFO("SM5 support available.\n");
949 if (dev_priv->sm_type == VMW_SM_4_1)
950 DRM_INFO("SM4_1 support available.\n");
951 if (dev_priv->sm_type == VMW_SM_4)
952 DRM_INFO("SM4 support available.\n");
953
954 snprintf(host_log, sizeof(host_log), "vmwgfx: %s-%s",
955 VMWGFX_REPO, VMWGFX_GIT_VERSION);
956 vmw_host_log(host_log);
957
958 memset(host_log, 0, sizeof(host_log));
959 snprintf(host_log, sizeof(host_log), "vmwgfx: Module Version: %d.%d.%d",
960 VMWGFX_DRIVER_MAJOR, VMWGFX_DRIVER_MINOR,
961 VMWGFX_DRIVER_PATCHLEVEL);
962 vmw_host_log(host_log);
963
964 if (dev_priv->enable_fb) {
965 vmw_fifo_resource_inc(dev_priv);
966 vmw_svga_enable(dev_priv);
967 vmw_fb_init(dev_priv);
968 }
969
970 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;
971 register_pm_notifier(&dev_priv->pm_nb);
972
973 return 0;
974
975 out_no_fifo:
976 vmw_overlay_close(dev_priv);
977 vmw_kms_close(dev_priv);
978 out_no_kms:
979 if (dev_priv->has_mob)
980 vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB);
981 if (dev_priv->has_gmr)
982 vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR);
983 vmw_vram_manager_fini(dev_priv);
984 out_no_vram:
985 (void)ttm_bo_device_release(&dev_priv->bdev);
986 out_no_bdev:
987 vmw_fence_manager_takedown(dev_priv->fman);
988 out_no_fman:
989 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
990 vmw_irq_uninstall(&dev_priv->drm);
991 out_no_irq:
992 pci_release_regions(dev_priv->drm.pdev);
993 out_no_device:
994 ttm_object_device_release(&dev_priv->tdev);
995 out_err4:
996 memunmap(dev_priv->mmio_virt);
997 out_err0:
998 for (i = vmw_res_context; i < vmw_res_max; ++i)
999 idr_destroy(&dev_priv->res_idr[i]);
1000
1001 if (dev_priv->ctx.staged_bindings)
1002 vmw_binding_state_free(dev_priv->ctx.staged_bindings);
1003 kfree(dev_priv);
1004 return ret;
1005 }
1006
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
-------------- next part --------------
A non-text attachment was scrubbed...
Name: .config.gz
Type: application/gzip
Size: 45459 bytes
Desc: not available
URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20201202/0ecafc47/attachment-0001.gz>
More information about the dri-devel
mailing list