[PATCH v4 16/16] drm/i915: Enable PCON configuration for Color Conversion for TGL

[Ankit Nautiyal]

This patch enables PCON configuration for color space conversion for
TGL+ platfrom. This will help in supporting 8k at 60 YUV420 modes common
in HDMI 8k panels, through a capable PCON.
Also allow 8k at 60 YUV420 modes, only if PCON claims to support the
color space conversion.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
 drivers/gpu/drm/i915/display/intel_dp.c  | 5 +++++
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 721a47bbc009..ed6b8ea85408 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3644,6 +3644,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
 	if (!is_mst)
 		intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
 
+	intel_dp_configure_protocol_converter(intel_dp);
 	intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
 	/*
 	 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index b3f1190d8150..86289c925612 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -720,6 +720,11 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector,
 	const struct drm_display_info *info = &connector->base.display_info;
 	int tmds_clock;
 
+	/* Allow 8k YUV420 modes, only if PCON supports RGB->YUV conversion */
+	if (mode->hdisplay == 7680 && drm_mode_is_420_only(info, mode) &&
+	    !intel_dp->dfp.rgb_to_ycbcr)
+		return MODE_NO_420;
+
 	/*
 	 * If PCON and HDMI2.1 sink both support FRL MODE, check FRL
 	 * bandwidth constraints.
-- 
2.17.1