[PATCH 2/8] drm/vc4: dsi: Correct DSI register definition

[Frieder Schrempf]

Hi Maxime,

On 03.12.20 14:25, Maxime Ripard wrote:
> From: Dave Stevenson <dave.stevenson at raspberrypi.com>
> 
> The DSI1_PHY_AFEC0_PD_DLANE1 and DSI1_PHY_AFEC0_PD_DLANE3 register
> definitions were swapped, so trying to use more than a single data
> lane failed as lane 1 would get powered down.
> (In theory a 4 lane device would work as all lanes would remain
> powered).
> 
> Correct the definitions.
> 
> Signed-off-by: Dave Stevenson <dave.stevenson at raspberrypi.com>
> Signed-off-by: Maxime Ripard <maxime at cerno.tech>

Wouldn't this deserve a "Fixes: ..." and "Cc: stable at vger.kernel.org" 
tag, as this bug is present in all stable releases since this driver was 
introduced? I think it would be really helpful to have it backported.

Thanks
Frieder

> ---
>   drivers/gpu/drm/vc4/vc4_dsi.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/vc4/vc4_dsi.c b/drivers/gpu/drm/vc4/vc4_dsi.c
> index b1d8765795f1..bb316e6cc12b 100644
> --- a/drivers/gpu/drm/vc4/vc4_dsi.c
> +++ b/drivers/gpu/drm/vc4/vc4_dsi.c
> @@ -306,11 +306,11 @@
>   # define DSI0_PHY_AFEC0_RESET			BIT(11)
>   # define DSI1_PHY_AFEC0_PD_BG			BIT(11)
>   # define DSI0_PHY_AFEC0_PD			BIT(10)
> -# define DSI1_PHY_AFEC0_PD_DLANE3		BIT(10)
> +# define DSI1_PHY_AFEC0_PD_DLANE1		BIT(10)
>   # define DSI0_PHY_AFEC0_PD_BG			BIT(9)
>   # define DSI1_PHY_AFEC0_PD_DLANE2		BIT(9)
>   # define DSI0_PHY_AFEC0_PD_DLANE1		BIT(8)
> -# define DSI1_PHY_AFEC0_PD_DLANE1		BIT(8)
> +# define DSI1_PHY_AFEC0_PD_DLANE3		BIT(8)
>   # define DSI_PHY_AFEC0_PTATADJ_MASK		VC4_MASK(7, 4)
>   # define DSI_PHY_AFEC0_PTATADJ_SHIFT		4
>   # define DSI_PHY_AFEC0_CTATADJ_MASK		VC4_MASK(3, 0)
>