[PATCH 1/2] drm/dp: Add PHY_TEST_PATTERN CP2520 Pattern 2 and 3

[Manasi Navare]

On Mon, Jul 20, 2020 at 05:40:10PM -0700, Almahallawy, Khaled wrote:
> On Mon, 2020-07-20 at 17:07 -0700, Manasi Navare wrote:
> > On Mon, Jul 20, 2020 at 04:41:25PM -0700, Khaled Almahallawy wrote:
> > > Add the missing CP2520 pattern 2 and 3 phy compliance patterns
> > >
> > > Signed-off-by: Khaled Almahallawy <khaled.almahallawy at intel.com>
> > > ---
> > >  drivers/gpu/drm/drm_dp_helper.c | 2 +-
> > >  include/drm/drm_dp_helper.h     | 4 +++-
> > >  2 files changed, 4 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/drm_dp_helper.c
> > > b/drivers/gpu/drm/drm_dp_helper.c
> > > index a3c82e726057..d0fb78c6aca6 100644
> > > --- a/drivers/gpu/drm/drm_dp_helper.c
> > > +++ b/drivers/gpu/drm/drm_dp_helper.c
> > > @@ -1583,7 +1583,7 @@ int drm_dp_get_phy_test_pattern(struct
> > > drm_dp_aux *aux,
> > >  return err;
> > >
> > >  break;
> > > -case DP_PHY_TEST_PATTERN_CP2520:
> > > +case DP_PHY_TEST_PATTERN_CP2520_PAT1:
> > >  err = drm_dp_dpcd_read(aux,
> > > DP_TEST_HBR2_SCRAMBLER_RESET,
> > >         &data->hbr2_reset,
> > >         sizeof(data->hbr2_reset));
> >
> > Where do we read PAT2 and PAT3, I see you defined those newly and
> > patch 2/2 has them
> > in teh switch case but the drm_dp_get_phy_test_pattern function
> > doesnt read them?
> >
> 
> Per my understanding from the specs, only HBR2 (CP2520 PAT1) requires
> reading dpcd address 0024Ah to set HBR2_COMPLIANCT_SCRAMBLER_RESET.
> TPS4 (CP2520 PAT3) doesn’t require that.
> I’m not sure about CP2520 PAT2 if it has use or not. In the test scope
> we can select 6 patterns. PAT2 is not one of them.
> 
> Thanks
> ~Khaled

Okay got it, with that

Reviewed-by: Manasi Navare <manasi.d.navare at intel.com>

Manasi

> 
> > Manasi
> >
> > > diff --git a/include/drm/drm_dp_helper.h
> > > b/include/drm/drm_dp_helper.h
> > > index e47dc22ebf50..65dd6cd71f1e 100644
> > > --- a/include/drm/drm_dp_helper.h
> > > +++ b/include/drm/drm_dp_helper.h
> > > @@ -708,7 +708,9 @@
> > >  # define DP_PHY_TEST_PATTERN_ERROR_COUNT    0x2
> > >  # define DP_PHY_TEST_PATTERN_PRBS7          0x3
> > >  # define DP_PHY_TEST_PATTERN_80BIT_CUSTOM   0x4
> > > -# define DP_PHY_TEST_PATTERN_CP2520         0x5
> > > +# define DP_PHY_TEST_PATTERN_CP2520_PAT10x5
> > > +# define DP_PHY_TEST_PATTERN_CP2520_PAT20x6
> > > +# define DP_PHY_TEST_PATTERN_CP2520_PAT30x7
> > >
> > >  #define DP_TEST_HBR2_SCRAMBLER_RESET        0x24A
> > >  #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0    0x250
> > > --
> > > 2.17.1
> > >