[PATCH 3/9] drm/radeon: stop implementing init_mem_type
daniel at ffwll.ch
daniel at ffwll.ch
Mon Jul 27 10:30:00 UTC 2020
On Thu, Jul 23, 2020 at 05:16:15PM +0200, Christian König wrote:
> Instead just initialize the memory type parameters
> before calling ttm_bo_init_mm.
>
> Signed-off-by: Christian König <christian.koenig at amd.com>
Hm what's the motivation here? I do agree that the init_mem_type callback
is rather midlayer-y (having a per-type cast in a callback is a very clear
signal something with the layering is all busted). So removing this sounds
like a good idea, but not really following why just for radeon? Or simply
wip?
-Daniel
> ---
> drivers/gpu/drm/radeon/radeon_ttm.c | 70 ++++++++++++++---------------
> 1 file changed, 35 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c
> index 9aba18a143e7..b0b59c553785 100644
> --- a/drivers/gpu/drm/radeon/radeon_ttm.c
> +++ b/drivers/gpu/drm/radeon/radeon_ttm.c
> @@ -69,43 +69,43 @@ struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev)
> static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
> struct ttm_mem_type_manager *man)
> {
> - struct radeon_device *rdev;
> + return 0;
> +}
>
> - rdev = radeon_get_rdev(bdev);
> +static int radeon_ttm_init_vram(struct radeon_device *rdev)
> +{
> + struct ttm_mem_type_manager *man = &rdev->mman.bdev.man[TTM_PL_VRAM];
>
> - switch (type) {
> - case TTM_PL_SYSTEM:
> - /* System memory */
> - break;
> - case TTM_PL_TT:
> - man->func = &ttm_bo_manager_func;
> - man->available_caching = TTM_PL_MASK_CACHING;
> - man->default_caching = TTM_PL_FLAG_CACHED;
> - man->use_tt = true;
> + man->func = &ttm_bo_manager_func;
> + man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
> + man->default_caching = TTM_PL_FLAG_WC;
> +
> + return ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM,
> + rdev->mc.real_vram_size >> PAGE_SHIFT);
> +}
> +
> +static int radeon_ttm_init_gtt(struct radeon_device *rdev)
> +{
> + struct ttm_mem_type_manager *man = &rdev->mman.bdev.man[TTM_PL_TT];
> +
> + man->func = &ttm_bo_manager_func;
> + man->available_caching = TTM_PL_MASK_CACHING;
> + man->default_caching = TTM_PL_FLAG_CACHED;
> + man->use_tt = true;
> #if IS_ENABLED(CONFIG_AGP)
> - if (rdev->flags & RADEON_IS_AGP) {
> - if (!rdev->ddev->agp) {
> - DRM_ERROR("AGP is not enabled for memory type %u\n",
> - (unsigned)type);
> - return -EINVAL;
> - }
> - man->available_caching = TTM_PL_FLAG_UNCACHED |
> - TTM_PL_FLAG_WC;
> - man->default_caching = TTM_PL_FLAG_WC;
> + if (rdev->flags & RADEON_IS_AGP) {
> + if (!rdev->ddev->agp) {
> + DRM_ERROR("AGP is not enabled\n");
> + return -EINVAL;
> }
> -#endif
> - break;
> - case TTM_PL_VRAM:
> - /* "On-card" video ram */
> - man->func = &ttm_bo_manager_func;
> - man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
> + man->available_caching = TTM_PL_FLAG_UNCACHED |
> + TTM_PL_FLAG_WC;
> man->default_caching = TTM_PL_FLAG_WC;
> - break;
> - default:
> - DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
> - return -EINVAL;
> }
> - return 0;
> +#endif
> +
> + return ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT,
> + rdev->mc.gtt_size >> PAGE_SHIFT);
> }
>
> static void radeon_evict_flags(struct ttm_buffer_object *bo,
> @@ -778,8 +778,8 @@ int radeon_ttm_init(struct radeon_device *rdev)
> return r;
> }
> rdev->mman.initialized = true;
> - r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM,
> - rdev->mc.real_vram_size >> PAGE_SHIFT);
> +
> + r = radeon_ttm_init_vram(rdev);
> if (r) {
> DRM_ERROR("Failed initializing VRAM heap.\n");
> return r;
> @@ -804,8 +804,8 @@ int radeon_ttm_init(struct radeon_device *rdev)
> }
> DRM_INFO("radeon: %uM of VRAM memory ready\n",
> (unsigned) (rdev->mc.real_vram_size / (1024 * 1024)));
> - r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT,
> - rdev->mc.gtt_size >> PAGE_SHIFT);
> +
> + r = radeon_ttm_init_gtt(rdev);
> if (r) {
> DRM_ERROR("Failed initializing GTT heap.\n");
> return r;
> --
> 2.17.1
>
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--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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