[radeon-alex:amd-staging-drm-next 9951/9999] drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c:243:16: sparse: sparse: cast to restricted __le32
kernel test robot
lkp at intel.com
Fri Jun 26 00:23:49 UTC 2020
Hi Sonny,
First bad commit (maybe != root cause):
tree: git://people.freedesktop.org/~agd5f/linux.git amd-staging-drm-next
head: cd5dd023c24f097393cd351bfaaba81284d1a15b
commit: 788c2ef8c423ccd8c62a471c7e7debe115b3e124 [9951/9999] drm amdgpu: SI UVD add uvd_v3_1 to makefile
config: s390-randconfig-s032-20200624 (attached as .config)
compiler: s390-linux-gcc (GCC) 9.3.0
reproduce:
# apt-get install sparse
# sparse version: v0.6.2-dirty
git checkout 788c2ef8c423ccd8c62a471c7e7debe115b3e124
# save the attached .config to linux build tree
make W=1 C=1 ARCH=s390 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__'
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp at intel.com>
sparse warnings: (new ones prefixed by >>)
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/oss/oss_1_0_sh_mask.h:26:9: sparse: sparse: preprocessor token CC_DRM_ID_STRAPS__ATI_REV_ID_MASK redefined
drivers/gpu/drm/amd/amdgpu/sid.h:2471:9: sparse: this was the original definition
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/oss/oss_1_0_sh_mask.h:27:9: sparse: sparse: preprocessor token CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT redefined
drivers/gpu/drm/amd/amdgpu/sid.h:2472:9: sparse: this was the original definition
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/oss/oss_1_0_sh_mask.h:744:9: sparse: sparse: preprocessor token IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK redefined
drivers/gpu/drm/amd/amdgpu/sid.h:2345:9: sparse: this was the original definition
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/oss/oss_1_0_sh_mask.h:760:9: sparse: sparse: preprocessor token IH_RB_WPTR__RB_OVERFLOW_MASK redefined
drivers/gpu/drm/amd/amdgpu/sid.h:2344:9: sparse: this was the original definition
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/oss/oss_1_0_sh_mask.h:988:9: sparse: sparse: preprocessor token SRBM_SOFT_RESET__SOFT_RESET_IH_MASK redefined
drivers/gpu/drm/amd/amdgpu/sid.h:2347:9: sparse: this was the original definition
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/oss/oss_1_0_sh_mask.h:1028:9: sparse: sparse: preprocessor token SRBM_STATUS__IH_BUSY_MASK redefined
drivers/gpu/drm/amd/amdgpu/sid.h:2346:9: sparse: this was the original definition
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/oss/oss_1_0_sh_mask.h:1032:9: sparse: sparse: preprocessor token SRBM_STATUS__MCB_BUSY_MASK redefined
drivers/gpu/drm/amd/amdgpu/sid.h:2435:9: sparse: this was the original definition
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/oss/oss_1_0_sh_mask.h:1033:9: sparse: sparse: preprocessor token SRBM_STATUS__MCB_BUSY__SHIFT redefined
drivers/gpu/drm/amd/amdgpu/sid.h:2436:9: sparse: this was the original definition
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/oss/oss_1_0_sh_mask.h:1034:9: sparse: sparse: preprocessor token SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK redefined
drivers/gpu/drm/amd/amdgpu/sid.h:2437:9: sparse: this was the original definition
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/oss/oss_1_0_sh_mask.h:1035:9: sparse: sparse: preprocessor token SRBM_STATUS__MCB_NON_DISPLAY_BUSY__SHIFT redefined
drivers/gpu/drm/amd/amdgpu/sid.h:2438:9: sparse: this was the original definition
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/oss/oss_1_0_sh_mask.h:1036:9: sparse: sparse: preprocessor token SRBM_STATUS__MCC_BUSY_MASK redefined
drivers/gpu/drm/amd/amdgpu/sid.h:2439:9: sparse: this was the original definition
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/oss/oss_1_0_sh_mask.h:1037:9: sparse: sparse: preprocessor token SRBM_STATUS__MCC_BUSY__SHIFT redefined
drivers/gpu/drm/amd/amdgpu/sid.h:2440:9: sparse: this was the original definition
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/oss/oss_1_0_sh_mask.h:1038:9: sparse: sparse: preprocessor token SRBM_STATUS__MCD_BUSY_MASK redefined
drivers/gpu/drm/amd/amdgpu/sid.h:2441:9: sparse: this was the original definition
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/oss/oss_1_0_sh_mask.h:1039:9: sparse: sparse: preprocessor token SRBM_STATUS__MCD_BUSY__SHIFT redefined
drivers/gpu/drm/amd/amdgpu/sid.h:2442:9: sparse: this was the original definition
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/oss/oss_1_0_sh_mask.h:1048:9: sparse: sparse: preprocessor token SRBM_STATUS__VMC_BUSY_MASK redefined
drivers/gpu/drm/amd/amdgpu/sid.h:2443:9: sparse: this was the original definition
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/oss/oss_1_0_sh_mask.h:1049:9: sparse: sparse: preprocessor token SRBM_STATUS__VMC_BUSY__SHIFT redefined
drivers/gpu/drm/amd/amdgpu/sid.h:2444:9: sparse: this was the original definition
>> drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c:243:16: sparse: sparse: cast to restricted __le32
>> drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c:243:16: sparse: sparse: cast to restricted __le32
>> drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c:243:16: sparse: sparse: cast to restricted __le32
>> drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c:243:16: sparse: sparse: cast to restricted __le32
>> drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c:243:16: sparse: sparse: cast to restricted __le32
>> drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c:243:16: sparse: sparse: cast to restricted __le32
vim +243 drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
6f4ae872ee40de Sonny Jiang 2020-06-10 228
6f4ae872ee40de Sonny Jiang 2020-06-10 229 /**
6f4ae872ee40de Sonny Jiang 2020-06-10 230 * uvd_v3_1_mc_resume - memory controller programming
6f4ae872ee40de Sonny Jiang 2020-06-10 231 *
6f4ae872ee40de Sonny Jiang 2020-06-10 232 * @adev: amdgpu_device pointer
6f4ae872ee40de Sonny Jiang 2020-06-10 233 *
6f4ae872ee40de Sonny Jiang 2020-06-10 234 * Let the UVD memory controller know it's offsets
6f4ae872ee40de Sonny Jiang 2020-06-10 235 */
6f4ae872ee40de Sonny Jiang 2020-06-10 236 static void uvd_v3_1_mc_resume(struct amdgpu_device *adev)
6f4ae872ee40de Sonny Jiang 2020-06-10 237 {
6f4ae872ee40de Sonny Jiang 2020-06-10 238 uint64_t addr;
6f4ae872ee40de Sonny Jiang 2020-06-10 239 uint32_t size;
6f4ae872ee40de Sonny Jiang 2020-06-10 240
6f4ae872ee40de Sonny Jiang 2020-06-10 241 /* programm the VCPU memory controller bits 0-27 */
6f4ae872ee40de Sonny Jiang 2020-06-10 242 addr = (adev->uvd.inst->gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3;
6f4ae872ee40de Sonny Jiang 2020-06-10 @243 size = AMDGPU_UVD_FIRMWARE_SIZE(adev) >> 3;
6f4ae872ee40de Sonny Jiang 2020-06-10 244 WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr);
6f4ae872ee40de Sonny Jiang 2020-06-10 245 WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
6f4ae872ee40de Sonny Jiang 2020-06-10 246
6f4ae872ee40de Sonny Jiang 2020-06-10 247 addr += size;
6f4ae872ee40de Sonny Jiang 2020-06-10 248 size = AMDGPU_UVD_HEAP_SIZE >> 3;
6f4ae872ee40de Sonny Jiang 2020-06-10 249 WREG32(mmUVD_VCPU_CACHE_OFFSET1, addr);
6f4ae872ee40de Sonny Jiang 2020-06-10 250 WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
6f4ae872ee40de Sonny Jiang 2020-06-10 251
6f4ae872ee40de Sonny Jiang 2020-06-10 252 addr += size;
6f4ae872ee40de Sonny Jiang 2020-06-10 253 size = (AMDGPU_UVD_STACK_SIZE +
6f4ae872ee40de Sonny Jiang 2020-06-10 254 (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles)) >> 3;
6f4ae872ee40de Sonny Jiang 2020-06-10 255 WREG32(mmUVD_VCPU_CACHE_OFFSET2, addr);
6f4ae872ee40de Sonny Jiang 2020-06-10 256 WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
6f4ae872ee40de Sonny Jiang 2020-06-10 257
6f4ae872ee40de Sonny Jiang 2020-06-10 258 /* bits 28-31 */
6f4ae872ee40de Sonny Jiang 2020-06-10 259 addr = (adev->uvd.inst->gpu_addr >> 28) & 0xF;
6f4ae872ee40de Sonny Jiang 2020-06-10 260 WREG32(mmUVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));
6f4ae872ee40de Sonny Jiang 2020-06-10 261
6f4ae872ee40de Sonny Jiang 2020-06-10 262 /* bits 32-39 */
6f4ae872ee40de Sonny Jiang 2020-06-10 263 addr = (adev->uvd.inst->gpu_addr >> 32) & 0xFF;
6f4ae872ee40de Sonny Jiang 2020-06-10 264 WREG32(mmUVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
6f4ae872ee40de Sonny Jiang 2020-06-10 265
6f4ae872ee40de Sonny Jiang 2020-06-10 266 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
6f4ae872ee40de Sonny Jiang 2020-06-10 267 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
6f4ae872ee40de Sonny Jiang 2020-06-10 268 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
6f4ae872ee40de Sonny Jiang 2020-06-10 269 }
6f4ae872ee40de Sonny Jiang 2020-06-10 270
:::::: The code at line 243 was first introduced by commit
:::::: 6f4ae872ee40de1d15b1808b207f4a39100025aa drm amdgpu: SI UVD v3_1
:::::: TO: Sonny Jiang <sonny.jiang at amd.com>
:::::: CC: Sonny Jiang <sonny.jiang at amd.com>
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
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