[PATCH v9 1/2] dt-bindings: display/bridge: Add binding for NWL mipi dsi host controller
Sam Ravnborg
sam at ravnborg.org
Wed Mar 18 21:47:31 UTC 2020
On Wed, Mar 18, 2020 at 04:09:07PM +0100, Guido Günther wrote:
> The Northwest Logic MIPI DSI IP core can be found in NXPs i.MX8 SoCs.
>
> Signed-off-by: Guido Günther <agx at sigxcpu.org>
> Tested-by: Robert Chiras <robert.chiras at nxp.com>
> Reviewed-by: Rob Herring <robh at kernel.org>
Acked-by: Sam Ravnborg <sam at ravnborg.org>
> ---
> .../bindings/display/bridge/nwl-dsi.yaml | 216 ++++++++++++++++++
> 1 file changed, 216 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml b/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml
> new file mode 100644
> index 000000000000..ec1e7e12719d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml
> @@ -0,0 +1,216 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/bridge/nwl-dsi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Northwest Logic MIPI-DSI controller on i.MX SoCs
> +
> +maintainers:
> + - Guido Gúnther <agx at sigxcpu.org>
> + - Robert Chiras <robert.chiras at nxp.com>
> +
> +description: |
> + NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for
> + the SOCs NWL MIPI-DSI host controller.
> +
> +properties:
> + compatible:
> + const: fsl,imx8mq-nwl-dsi
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + '#address-cells':
> + const: 1
> +
> + '#size-cells':
> + const: 0
> +
> + clocks:
> + items:
> + - description: DSI core clock
> + - description: RX_ESC clock (used in escape mode)
> + - description: TX_ESC clock (used in escape mode)
> + - description: PHY_REF clock
> + - description: LCDIF clock
> +
> + clock-names:
> + items:
> + - const: core
> + - const: rx_esc
> + - const: tx_esc
> + - const: phy_ref
> + - const: lcdif
> +
> + mux-controls:
> + description:
> + mux controller node to use for operating the input mux
> +
> + phys:
> + maxItems: 1
> + description:
> + A phandle to the phy module representing the DPHY
> +
> + phy-names:
> + items:
> + - const: dphy
> +
> + power-domains:
> + maxItems: 1
> +
> + resets:
> + items:
> + - description: dsi byte reset line
> + - description: dsi dpi reset line
> + - description: dsi esc reset line
> + - description: dsi pclk reset line
> +
> + reset-names:
> + items:
> + - const: byte
> + - const: dpi
> + - const: esc
> + - const: pclk
> +
> + ports:
> + type: object
> + description:
> + A node containing DSI input & output port nodes with endpoint
> + definitions as documented in
> + Documentation/devicetree/bindings/graph.txt.
> + properties:
> + port at 0:
> + type: object
> + description:
> + Input port node to receive pixel data from the
> + display controller. Exactly one endpoint must be
> + specified.
> + properties:
> + '#address-cells':
> + const: 1
> +
> + '#size-cells':
> + const: 0
> +
> + endpoint at 0:
> + description: sub-node describing the input from LCDIF
> + type: object
> +
> + endpoint at 1:
> + description: sub-node describing the input from DCSS
> + type: object
> +
> + reg:
> + const: 0
> +
> + required:
> + - '#address-cells'
> + - '#size-cells'
> + - reg
> + additionalProperties: false
> +
> + port at 1:
> + type: object
> + description:
> + DSI output port node to the panel or the next bridge
> + in the chain
> +
> + '#address-cells':
> + const: 1
> +
> + '#size-cells':
> + const: 0
> +
> + required:
> + - '#address-cells'
> + - '#size-cells'
> + - port at 0
> + - port at 1
> +
> + additionalProperties: false
> +
> +patternProperties:
> + "^panel@[0-9]+$":
> + type: object
> +
> +required:
> + - '#address-cells'
> + - '#size-cells'
> + - clock-names
> + - clocks
> + - compatible
> + - interrupts
> + - mux-controls
> + - phy-names
> + - phys
> + - ports
> + - reg
> + - reset-names
> + - resets
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> +
> + #include <dt-bindings/clock/imx8mq-clock.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/reset/imx8mq-reset.h>
> +
> + mipi_dsi: mipi_dsi at 30a00000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,imx8mq-nwl-dsi";
> + reg = <0x30A00000 0x300>;
> + clocks = <&clk IMX8MQ_CLK_DSI_CORE>,
> + <&clk IMX8MQ_CLK_DSI_AHB>,
> + <&clk IMX8MQ_CLK_DSI_IPG_DIV>,
> + <&clk IMX8MQ_CLK_DSI_PHY_REF>,
> + <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
> + clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif";
> + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> + mux-controls = <&mux 0>;
> + power-domains = <&pgc_mipi>;
> + resets = <&src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N>,
> + <&src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N>,
> + <&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>,
> + <&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>;
> + reset-names = "byte", "dpi", "esc", "pclk";
> + phys = <&dphy>;
> + phy-names = "dphy";
> +
> + panel at 0 {
> + compatible = "rocktech,jh057n00900";
> + reg = <0>;
> + port at 0 {
> + panel_in: endpoint {
> + remote-endpoint = <&mipi_dsi_out>;
> + };
> + };
> + };
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port at 0 {
> + #size-cells = <0>;
> + #address-cells = <1>;
> + reg = <0>;
> + mipi_dsi_in: endpoint at 0 {
> + reg = <0>;
> + remote-endpoint = <&lcdif_mipi_dsi>;
> + };
> + };
> + port at 1 {
> + reg = <1>;
> + mipi_dsi_out: endpoint {
> + remote-endpoint = <&panel_in>;
> + };
> + };
> + };
> + };
> --
> 2.23.0
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