[PATCH v3 015/105] drm/vc4: hvs: Boost the core clock during modeset

[Eric Anholt]

On Wed, May 27, 2020 at 8:49 AM Maxime Ripard <maxime at cerno.tech> wrote:
>
> In order to prevent timeouts and stalls in the pipeline, the core clock
> needs to be maxed at 500MHz during a modeset on the BCM2711.

Like, the whole system's core clock?  How is it reasonable for some
device driver to crank the system's core clock up and back down to
some fixed-in-the-driver frequency?  Sounds like you need some sort of
opp thing here.

Patch 13,14 r-b.