[PATCH v3 032/105] drm/vc4: crtc: Enable and disable the PV in atomic_enable / disable

Eric Anholt eric at anholt.net
Wed May 27 16:54:44 UTC 2020

On Wed, May 27, 2020 at 8:50 AM Maxime Ripard <maxime at cerno.tech> wrote:
> The VIDEN bit in the pixelvalve currently being used to enable or disable
> the pixelvalve seems to not be enough in some situations, which whill end
> up with the pixelvalve stalling.
> In such a case, even re-enabling VIDEN doesn't bring it back and we need to
> clear the FIFO. This can only be done if the pixelvalve is disabled though.
> In order to overcome this, we can configure the pixelvalve during
> mode_set_no_fb, but only enable it in atomic_enable and flush the FIFO
> there, and in atomic_disable disable the pixelvalve again.

What displays has this been tested with?  Getting this sequencing
right is so painful, and things like DSI are tricky to get to light

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