[Freedreno] [PATCH v2 3/4] drm/msm: register the base address with dpu_dbg module
Rob Clark
robdclark at gmail.com
Wed Nov 4 17:26:24 UTC 2020
On Thu, Oct 29, 2020 at 6:01 PM Abhinav Kumar <abhinavk at codeaurora.org> wrote:
>
> Register the base address of various dpu sub-modules with the
> dpu_dbg module so that it can be dumped out during error scenarios.
>
> changes in v2:
> - Fix an issue where the same dsi client was getting registered
> multiple times to the dpu_dbg module
>
> Signed-off-by: Abhinav Kumar <abhinavk at codeaurora.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.c | 4 +--
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 6 ++++-
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c | 7 +++--
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 5 +++-
> .../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 6 ++++-
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 8 +++++-
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 7 ++++-
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 12 +++++++--
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 4 ++-
> drivers/gpu/drm/msm/dp/dp_catalog.c | 12 +++++++++
> drivers/gpu/drm/msm/dp/dp_catalog.h | 4 +++
> drivers/gpu/drm/msm/dp/dp_display.c | 2 ++
> drivers/gpu/drm/msm/dsi/dsi.c | 1 +
> drivers/gpu/drm/msm/dsi/dsi.h | 1 +
> drivers/gpu/drm/msm/dsi/dsi_host.c | 15 ++++++++++-
> drivers/gpu/drm/msm/msm_drv.c | 26 ++++++++++++++++++-
> drivers/gpu/drm/msm/msm_drv.h | 3 ++-
> 17 files changed, 108 insertions(+), 15 deletions(-)
>
[snip]
> diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
> index f6fb0187388f..df505a3d53e8 100644
> --- a/drivers/gpu/drm/msm/msm_drv.c
> +++ b/drivers/gpu/drm/msm/msm_drv.c
> @@ -17,8 +17,8 @@
> #include <drm/drm_prime.h>
> #include <drm/drm_of.h>
> #include <drm/drm_vblank.h>
> -#include "dpu_dbg.h"
>
> +#include "dpu_dbg.h"
> #include "msm_drv.h"
> #include "msm_debugfs.h"
> #include "msm_fence.h"
> @@ -166,6 +166,24 @@ void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name,
> return _msm_ioremap(pdev, name, dbgname, true);
> }
>
> +unsigned long msm_iomap_size(struct platform_device *pdev, const char *name)
> +{
> + struct resource *res;
> +
> + if (name)
> + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
> + else
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +
> + if (!res) {
> + dev_dbg(&pdev->dev, "failed to get memory resource: %s\n",
> + name);
> + return 0;
> + }
> +
> + return resource_size(res);
> +}
> +
> void msm_writel(u32 data, void __iomem *addr)
> {
> if (reglog)
> @@ -535,6 +553,8 @@ static int msm_drm_init(struct device *dev, struct drm_driver *drv)
> if (ret)
> goto err_msm_uninit;
>
> + dpu_dbg_register_drm_dev(ddev);
> +
> drm_mode_config_reset(ddev);
>
> #ifdef CONFIG_DRM_FBDEV_EMULATION
> @@ -1282,6 +1302,10 @@ static int msm_pdev_probe(struct platform_device *pdev)
> int ret;
>
> if (get_mdp_ver(pdev)) {
> + ret = dpu_dbg_init(&pdev->dev);
> + if (ret)
> + pr_err("dpu_dbg_init failed ret = %d\n", ret);
> +
> ret = add_display_components(&pdev->dev, &match);
> if (ret)
> return ret;
I'm a bit skeptical about where you are registering/initializing dpu
dbg.. what happens on mdp4/mdp5 devices?
BR,
-R
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