[radeon-alex:drm-next 12/94] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_dccg.c:46:6: warning: no previous prototype for function 'dccg21_update_dpp_dto'

[kernel test robot]

tree:   git://people.freedesktop.org/~agd5f/linux.git drm-next
head:   d99bd826bd53b4dd02219834e6fff7833c3c1ba0
commit: c07cbc1f04ecba00f99e313de3190db5e7438e81 [12/94] drm/amd/display: update dpp dto phase and modulo.
config: arm64-randconfig-r003-20201113 (attached as .config)
compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project 9e0c35655b6e8186baef8840b26ba4090503b554)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # install arm64 cross compiling tool for clang build
        # apt-get install binutils-aarch64-linux-gnu
        git remote add radeon-alex git://people.freedesktop.org/~agd5f/linux.git
        git fetch --no-tags radeon-alex drm-next
        git checkout c07cbc1f04ecba00f99e313de3190db5e7438e81
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=arm64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp at intel.com>

All warnings (new ones prefixed by >>):

>> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_dccg.c:46:6: warning: no previous prototype for function 'dccg21_update_dpp_dto' [-Wmissing-prototypes]
   void dccg21_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk)
        ^
   drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_dccg.c:46:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
   void dccg21_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk)
   ^
   static 
   1 warning generated.

vim +/dccg21_update_dpp_dto +46 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_dccg.c

    30	
    31	#define TO_DCN_DCCG(dccg)\
    32		container_of(dccg, struct dcn_dccg, base)
    33	
    34	#define REG(reg) \
    35		(dccg_dcn->regs->reg)
    36	
    37	#undef FN
    38	#define FN(reg_name, field_name) \
    39		dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
    40	
    41	#define CTX \
    42		dccg_dcn->base.ctx
    43	#define DC_LOGGER \
    44		dccg->ctx->logger
    45	
  > 46	void dccg21_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk)
    47	{
    48		struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
    49	
    50		if (dccg->ref_dppclk) {
    51			int ref_dppclk = dccg->ref_dppclk;
    52			int modulo = ref_dppclk / 10000;
    53	
    54			if (req_dppclk) {
    55				int phase;
    56	
    57				/*
    58				 * program DPP DTO phase and modulo as below
    59				 * phase = dpp_pipe_clk_mhz / 10
    60				 * module = dpp_global_clk_mhz / 10
    61				 * dmub FW will read phase value to
    62				 * determine minimum dpp clk and notify smu
    63				 * to set clks for more power saving in PSR state
    64				 */
    65				phase = (req_dppclk + 9999) / 10000;
    66	
    67				if (phase > 0xff) {
    68					ASSERT(false);
    69					phase = 0xff;
    70				}
    71	
    72				REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
    73						DPPCLK0_DTO_PHASE, phase,
    74						DPPCLK0_DTO_MODULO, modulo);
    75				REG_UPDATE(DPPCLK_DTO_CTRL,
    76						DPPCLK_DTO_ENABLE[dpp_inst], 1);
    77			} else {
    78				/*
    79				 *  set phase to 10 if dpp isn't used to
    80				 *  prevent hard hang if access dpp register
    81				 *  on unused pipe
    82				 */
    83				REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
    84					DPPCLK0_DTO_PHASE, 10,
    85					DPPCLK0_DTO_MODULO, modulo);
    86	
    87				REG_UPDATE(DPPCLK_DTO_CTRL,
    88					DPPCLK_DTO_ENABLE[dpp_inst], 0);
    89			}
    90		}
    91	
    92		dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk;
    93	}
    94	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
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