next/master bisection: baseline.dmesg.emerg on meson-gxbb-p200

[Marc Zyngier]

On 2020-11-20 09:26, Neil Armstrong wrote:
> On 19/11/2020 19:35, Marc Zyngier wrote:
>>>>> diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c 
>>>>> b/drivers/gpu/drm/meson/meson_dw_hdmi.c
>>>>> index 7f8eea494147..52af8ba94311 100644
>>>>> --- a/drivers/gpu/drm/meson/meson_dw_hdmi.c
>>>>> +++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c
>>>>> @@ -146,6 +146,7 @@ struct meson_dw_hdmi {
>>>>>      struct reset_control *hdmitx_ctrl;
>>>>>      struct reset_control *hdmitx_phy;
>>>>>      struct clk *hdmi_pclk;
>>>>> +    struct clk *iahb_clk;
>>>>>      struct clk *venci_clk;
>>>>>      struct regulator *hdmi_supply;
>>>>>      u32 irq_stat;
>>>>> @@ -1033,6 +1034,13 @@ static int meson_dw_hdmi_bind(struct device 
>>>>> *dev, struct device *master,
>>>>>      }
>>>>>      clk_prepare_enable(meson_dw_hdmi->hdmi_pclk);
>>>>> 
>>>>> +    meson_dw_hdmi->iahb_clk = devm_clk_get(dev, "iahb");
>>>>> +    if (IS_ERR(meson_dw_hdmi->iahb_clk)) {
>>>>> +        dev_err(dev, "Unable to get iahb clk\n");
>>>>> +        return PTR_ERR(meson_dw_hdmi->iahb_clk);
>>>>> +    }
>>>>> +    clk_prepare_enable(meson_dw_hdmi->iahb_clk);
> 
> 
> On previous SoCs, iahb was directly the bus clock (clk81), and on 
> recent socs
> this clock is a gate.
> 
> The question is why is it disabled. Maybe a previous failed probe 
> disabled it
> in the dw-hdmi probe failure code and this clock is needed for
> meson_dw_hdmi_init(),
> so yeah this is the right fix.
> 
> Thanks.
> 
> Could you send a revert of b33340e33acdfe5ca6a5aa1244709575ae1e0432
> and then proper fix with clk_disable_unprepare added ?

Bah. I missed that email and sent a slightly different resolution.
Hopefully that'll be good enough.

Thanks,

         M.
-- 
Jazz is not dead. It just smells funny...