[PATCH v5 7/7] arm: dts: mt7623: add display subsystem related device nodes
Matthias Brugger
matthias.bgg at gmail.com
Wed Sep 9 09:29:36 UTC 2020
On 19/08/2020 10:17, Frank Wunderlich wrote:
> From: Ryder Lee <ryder.lee at mediatek.com>
>
> Add display subsystem related device nodes for MT7623.
>
> Cc: Chun-Kuang Hu <chunkuang.hu at kernel.org>
> Signed-off-by: chunhui dai <chunhui.dai at mediatek.com>
> Signed-off-by: Bibby Hsieh <bibby.hsieh at mediatek.com>
> Signed-off-by: Ryder Lee <ryder.lee at mediatek.com>
> Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
> Tested-by: Frank Wunderlich <frank-w at public-files.de>
Applied to v5.9-next/dts32
Thanks!
> ---
> changed
> v4->v5:
> add nodes to new mt7623n.dtsi to avoid conflict with mt7623a
> v3->v4:
> drop display_components which is duplicate of existing mmsys
> v2->v3:
> drop bls to dpi routing
> ---
> arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts | 72 ++++++++
> arch/arm/boot/dts/mt7623n-rfb-emmc.dts | 72 ++++++++
> arch/arm/boot/dts/mt7623n.dtsi | 171 ++++++++++++++++++
> 3 files changed, 315 insertions(+)
>
> diff --git a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
> index 344f8c65c4aa..f41f221e56ca 100644
> --- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
> +++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
> @@ -21,6 +21,19 @@ chosen {
> stdout-path = "serial2:115200n8";
> };
>
> + connector {
> + compatible = "hdmi-connector";
> + label = "hdmi";
> + type = "d";
> + ddc-i2c-bus = <&hdmiddc0>;
> +
> + port {
> + hdmi_connector_in: endpoint {
> + remote-endpoint = <&hdmi0_out>;
> + };
> + };
> + };
> +
> cpus {
> cpu at 0 {
> proc-supply = <&mt6323_vproc_reg>;
> @@ -114,10 +127,18 @@ memory at 80000000 {
> };
> };
>
> +&bls {
> + status = "okay";
> +};
> +
> &btif {
> status = "okay";
> };
>
> +&cec {
> + status = "okay";
> +};
> +
> &cir {
> pinctrl-names = "default";
> pinctrl-0 = <&cir_pins_a>;
> @@ -128,6 +149,21 @@ &crypto {
> status = "okay";
> };
>
> +&dpi0 {
> + status = "okay";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + port at 0 {
> + reg = <0>;
> + dpi0_out: endpoint {
> + remote-endpoint = <&hdmi0_in>;
> + };
> + };
> + };
> +};
> +
> ð {
> status = "okay";
>
> @@ -199,6 +235,42 @@ fixed-link {
> };
> };
>
> +&hdmi0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&hdmi_pins_a>;
> + status = "okay";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + port at 0 {
> + reg = <0>;
> + hdmi0_in: endpoint {
> + remote-endpoint = <&dpi0_out>;
> + };
> + };
> +
> + port at 1 {
> + reg = <1>;
> + hdmi0_out: endpoint {
> + remote-endpoint = <&hdmi_connector_in>;
> + };
> + };
> + };
> +};
> +
> +&hdmiddc0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&hdmi_ddc_pins_a>;
> + status = "okay";
> +};
> +
> +&hdmi_phy {
> + mediatek,ibias = <0xa>;
> + mediatek,ibias_up = <0x1c>;
> + status = "okay";
> +};
> +
> &i2c0 {
> pinctrl-names = "default";
> pinctrl-0 = <&i2c0_pins_a>;
> diff --git a/arch/arm/boot/dts/mt7623n-rfb-emmc.dts b/arch/arm/boot/dts/mt7623n-rfb-emmc.dts
> index f8efcc364bc3..1b9b9a8145a7 100644
> --- a/arch/arm/boot/dts/mt7623n-rfb-emmc.dts
> +++ b/arch/arm/boot/dts/mt7623n-rfb-emmc.dts
> @@ -24,6 +24,19 @@ chosen {
> stdout-path = "serial2:115200n8";
> };
>
> + connector {
> + compatible = "hdmi-connector";
> + label = "hdmi";
> + type = "d";
> + ddc-i2c-bus = <&hdmiddc0>;
> +
> + port {
> + hdmi_connector_in: endpoint {
> + remote-endpoint = <&hdmi0_out>;
> + };
> + };
> + };
> +
> cpus {
> cpu at 0 {
> proc-supply = <&mt6323_vproc_reg>;
> @@ -106,10 +119,18 @@ sound {
> };
> };
>
> +&bls {
> + status = "okay";
> +};
> +
> &btif {
> status = "okay";
> };
>
> +&cec {
> + status = "okay";
> +};
> +
> &cir {
> pinctrl-names = "default";
> pinctrl-0 = <&cir_pins_a>;
> @@ -120,6 +141,21 @@ &crypto {
> status = "okay";
> };
>
> +&dpi0 {
> + status = "okay";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + port at 0 {
> + reg = <0>;
> + dpi0_out: endpoint {
> + remote-endpoint = <&hdmi0_in>;
> + };
> + };
> + };
> +};
> +
> ð {
> status = "okay";
>
> @@ -203,6 +239,42 @@ fixed-link {
> };
> };
>
> +&hdmi0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&hdmi_pins_a>;
> + status = "okay";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + port at 0 {
> + reg = <0>;
> + hdmi0_in: endpoint {
> + remote-endpoint = <&dpi0_out>;
> + };
> + };
> +
> + port at 1 {
> + reg = <1>;
> + hdmi0_out: endpoint {
> + remote-endpoint = <&hdmi_connector_in>;
> + };
> + };
> + };
> +};
> +
> +&hdmiddc0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&hdmi_ddc_pins_a>;
> + status = "okay";
> +};
> +
> +&hdmi_phy {
> + mediatek,ibias = <0xa>;
> + mediatek,ibias_up = <0x1c>;
> + status = "okay";
> +};
> +
> &i2c0 {
> pinctrl-names = "default";
> pinctrl-0 = <&i2c0_pins_a>;
> diff --git a/arch/arm/boot/dts/mt7623n.dtsi b/arch/arm/boot/dts/mt7623n.dtsi
> index a47e82468895..61545fc541c4 100644
> --- a/arch/arm/boot/dts/mt7623n.dtsi
> +++ b/arch/arm/boot/dts/mt7623n.dtsi
> @@ -10,6 +10,10 @@
> #include <dt-bindings/memory/mt2701-larb-port.h>
>
> / {
> + aliases {
> + rdma0 = &rdma0;
> + rdma1 = &rdma1;
> + };
> g3dsys: syscon at 13000000 {
> compatible = "mediatek,mt7623-g3dsys",
> "mediatek,mt2701-g3dsys",
> @@ -131,4 +135,171 @@ smi_common: smi at 1000c000 {
> clock-names = "apb", "smi", "async";
> power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
> };
> +
> + ovl: ovl at 14007000 {
> + compatible = "mediatek,mt7623-disp-ovl",
> + "mediatek,mt2701-disp-ovl";
> + reg = <0 0x14007000 0 0x1000>;
> + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&mmsys CLK_MM_DISP_OVL>;
> + iommus = <&iommu MT2701_M4U_PORT_DISP_OVL_0>;
> + mediatek,larb = <&larb0>;
> + };
> +
> + rdma0: rdma at 14008000 {
> + compatible = "mediatek,mt7623-disp-rdma",
> + "mediatek,mt2701-disp-rdma";
> + reg = <0 0x14008000 0 0x1000>;
> + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&mmsys CLK_MM_DISP_RDMA>;
> + iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA>;
> + mediatek,larb = <&larb0>;
> + };
> +
> + wdma at 14009000 {
> + compatible = "mediatek,mt7623-disp-wdma",
> + "mediatek,mt2701-disp-wdma";
> + reg = <0 0x14009000 0 0x1000>;
> + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&mmsys CLK_MM_DISP_WDMA>;
> + iommus = <&iommu MT2701_M4U_PORT_DISP_WDMA>;
> + mediatek,larb = <&larb0>;
> + };
> +
> + bls: pwm at 1400a000 {
> + compatible = "mediatek,mt7623-disp-pwm",
> + "mediatek,mt2701-disp-pwm";
> + reg = <0 0x1400a000 0 0x1000>;
> + #pwm-cells = <2>;
> + clocks = <&mmsys CLK_MM_MDP_BLS_26M>,
> + <&mmsys CLK_MM_DISP_BLS>;
> + clock-names = "main", "mm";
> + status = "disabled";
> + };
> +
> + color: color at 1400b000 {
> + compatible = "mediatek,mt7623-disp-color",
> + "mediatek,mt2701-disp-color";
> + reg = <0 0x1400b000 0 0x1000>;
> + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&mmsys CLK_MM_DISP_COLOR>;
> + };
> +
> + dsi: dsi at 1400c000 {
> + compatible = "mediatek,mt7623-dsi",
> + "mediatek,mt2701-dsi";
> + reg = <0 0x1400c000 0 0x1000>;
> + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&mmsys CLK_MM_DSI_ENGINE>,
> + <&mmsys CLK_MM_DSI_DIG>,
> + <&mipi_tx0>;
> + clock-names = "engine", "digital", "hs";
> + phys = <&mipi_tx0>;
> + phy-names = "dphy";
> + status = "disabled";
> + };
> +
> + mutex: mutex at 1400e000 {
> + compatible = "mediatek,mt7623-disp-mutex",
> + "mediatek,mt2701-disp-mutex";
> + reg = <0 0x1400e000 0 0x1000>;
> + interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&mmsys CLK_MM_MUTEX_32K>;
> + };
> +
> + rdma1: rdma at 14012000 {
> + compatible = "mediatek,mt7623-disp-rdma",
> + "mediatek,mt2701-disp-rdma";
> + reg = <0 0x14012000 0 0x1000>;
> + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&mmsys CLK_MM_DISP_RDMA1>;
> + iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA1>;
> + mediatek,larb = <&larb0>;
> + };
> +
> + dpi0: dpi at 14014000 {
> + compatible = "mediatek,mt7623-dpi",
> + "mediatek,mt2701-dpi";
> + reg = <0 0x14014000 0 0x1000>;
> + interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&mmsys CLK_MM_DPI1_DIGL>,
> + <&mmsys CLK_MM_DPI1_ENGINE>,
> + <&apmixedsys CLK_APMIXED_TVDPLL>;
> + clock-names = "pixel", "engine", "pll";
> + status = "disabled";
> + };
> +
> + hdmi0: hdmi at 14015000 {
> + compatible = "mediatek,mt7623-hdmi",
> + "mediatek,mt8173-hdmi";
> + reg = <0 0x14015000 0 0x400>;
> + clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
> + <&mmsys CLK_MM_HDMI_PLL>,
> + <&mmsys CLK_MM_HDMI_AUDIO>,
> + <&mmsys CLK_MM_HDMI_SPDIF>;
> + clock-names = "pixel", "pll", "bclk", "spdif";
> + phys = <&hdmi_phy>;
> + phy-names = "hdmi";
> + mediatek,syscon-hdmi = <&mmsys 0x900>;
> + cec = <&cec>;
> + status = "disabled";
> + };
> +
> + mipi_tx0: mipi-dphy at 10010000 {
> + compatible = "mediatek,mt7623-mipi-tx",
> + "mediatek,mt2701-mipi-tx";
> + reg = <0 0x10010000 0 0x90>;
> + clocks = <&clk26m>;
> + clock-output-names = "mipi_tx0_pll";
> + #clock-cells = <0>;
> + #phy-cells = <0>;
> + };
> +
> + cec: cec at 10012000 {
> + compatible = "mediatek,mt7623-cec",
> + "mediatek,mt8173-cec";
> + reg = <0 0x10012000 0 0xbc>;
> + interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&infracfg CLK_INFRA_CEC>;
> + status = "disabled";
> + };
> +
> + hdmi_phy: phy at 10209100 {
> + compatible = "mediatek,mt7623-hdmi-phy",
> + "mediatek,mt2701-hdmi-phy";
> + reg = <0 0x10209100 0 0x24>;
> + clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
> + clock-names = "pll_ref";
> + clock-output-names = "hdmitx_dig_cts";
> + #clock-cells = <0>;
> + #phy-cells = <0>;
> + status = "disabled";
> + };
> +
> + hdmiddc0: i2c at 11013000 {
> + compatible = "mediatek,mt7623-hdmi-ddc",
> + "mediatek,mt8173-hdmi-ddc";
> + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
> + reg = <0 0x11013000 0 0x1C>;
> + clocks = <&pericfg CLK_PERI_I2C3>;
> + clock-names = "ddc-i2c";
> + status = "disabled";
> + };
> +};
> +
> +&pio {
> + hdmi_pins_a: hdmi-default {
> + pins-hdmi {
> + pinmux = <MT7623_PIN_123_HTPLG_FUNC_HTPLG>;
> + input-enable;
> + bias-pull-down;
> + };
> + };
> +
> + hdmi_ddc_pins_a: hdmi_ddc-default {
> + pins-hdmi-ddc {
> + pinmux = <MT7623_PIN_124_GPIO124_FUNC_HDMISCK>,
> + <MT7623_PIN_125_GPIO125_FUNC_HDMISD>;
> + };
> + };
> };
>
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