[PATCH] drm/bridge: dw-mipi-dsi: permit configuring the escape clock rate

[Philippe CORNU]

On 9/4/20 2:55 PM, Neil Armstrong wrote:
> The Amlogic D-PHY in the Amlogic AXG SoC Family does support a frequency
> higher than 10MHz for the TX Escape Clock, thus make the target rate
> configurable.
> 
> Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
> ---
>   drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 25 +++++++++++++++----
>   include/drm/bridge/dw_mipi_dsi.h              |  1 +
>   2 files changed, 21 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> index d580b2aa4ce9..31fc965c66fd 100644
> --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> @@ -562,15 +562,30 @@ static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)
>   
>   static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
>   {
> +	const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
> +	unsigned int esc_rate; /* in MHz */
> +	u32 esc_clk_division;
> +	int ret;
> +
>   	/*
>   	 * The maximum permitted escape clock is 20MHz and it is derived from
> -	 * lanebyteclk, which is running at "lane_mbps / 8".  Thus we want:
> -	 *
> -	 *     (lane_mbps >> 3) / esc_clk_division < 20
> +	 * lanebyteclk, which is running at "lane_mbps / 8".
> +	 */
> +	if (phy_ops->get_esc_clk_rate) {
> +		ret = phy_ops->get_esc_clk_rate(dsi->plat_data->priv_data,
> +						&esc_rate);
> +		if (ret)
> +			DRM_DEBUG_DRIVER("Phy get_esc_clk_rate() failed\n");
> +	} else
> +		esc_rate = 20; /* Default to 20MHz */
> +
> +	/*
> +	 * We want :
> +	 *     (lane_mbps >> 3) / esc_clk_division < X
>   	 * which is:
> -	 *     (lane_mbps >> 3) / 20 > esc_clk_division
> +	 *     (lane_mbps >> 3) / X > esc_clk_division
>   	 */
> -	u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1;
> +	esc_clk_division = (dsi->lane_mbps >> 3) / esc_rate + 1;
>   
>   	dsi_write(dsi, DSI_PWR_UP, RESET);
>   
> diff --git a/include/drm/bridge/dw_mipi_dsi.h b/include/drm/bridge/dw_mipi_dsi.h
> index b0e390b3288e..bda8aa7c2280 100644
> --- a/include/drm/bridge/dw_mipi_dsi.h
> +++ b/include/drm/bridge/dw_mipi_dsi.h
> @@ -36,6 +36,7 @@ struct dw_mipi_dsi_phy_ops {
>   			     unsigned int *lane_mbps);
>   	int (*get_timing)(void *priv_data, unsigned int lane_mbps,
>   			  struct dw_mipi_dsi_dphy_timing *timing);
> +	int (*get_esc_clk_rate)(void *priv_data, unsigned int *esc_clk_rate);
>   };
>   
>   struct dw_mipi_dsi_host_ops {
> 

Hi Neil,
Thank you for the patch

Reviewed-by: Philippe Cornu <philippe.cornu at st.com>

Philippe :-)