[Freedreno] [PATCH 06/11] drm/msm/disp/dpu1: Add DSC support in hw_ctl
abhinavk at codeaurora.org
abhinavk at codeaurora.org
Tue Aug 3 00:00:22 UTC 2021
On 2021-07-14 23:51, Vinod Koul wrote:
> Later gens of hardware have DSC bits moved to hw_ctl, so configure
> these
> bits so that DSC would work there as well
>
> Signed-off-by: Vinod Koul <vkoul at kernel.org>
Please correct me if wrong but here you seem to be flushing all the DSC
bits
even the unused ones. This will end-up enabling DSC even when DSC is
unused on
the newer targets.
If so, thats wrong.
We need to implement bit-mask based approach to avoid this change and
only enable
those DSCs which are used.
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> index 2d4645e01ebf..aeea6add61ee 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> @@ -25,6 +25,8 @@
> #define CTL_MERGE_3D_ACTIVE 0x0E4
> #define CTL_INTF_ACTIVE 0x0F4
> #define CTL_MERGE_3D_FLUSH 0x100
> +#define CTL_DSC_ACTIVE 0x0E8
> +#define CTL_DSC_FLUSH 0x104
> #define CTL_INTF_FLUSH 0x110
> #define CTL_INTF_MASTER 0x134
> #define CTL_FETCH_PIPE_ACTIVE 0x0FC
> @@ -34,6 +36,7 @@
>
> #define DPU_REG_RESET_TIMEOUT_US 2000
> #define MERGE_3D_IDX 23
> +#define DSC_IDX 22
> #define INTF_IDX 31
> #define CTL_INVALID_BIT 0xffff
>
> @@ -120,6 +123,7 @@ static u32 dpu_hw_ctl_get_pending_flush(struct
> dpu_hw_ctl *ctx)
>
> static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx)
> {
> + DPU_REG_WRITE(&ctx->hw, CTL_DSC_FLUSH, BIT(0) | BIT(1) | BIT(2) |
> BIT(3));
>
> if (ctx->pending_flush_mask & BIT(MERGE_3D_IDX))
> DPU_REG_WRITE(&ctx->hw, CTL_MERGE_3D_FLUSH,
> @@ -128,7 +132,7 @@ static inline void
> dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx)
> DPU_REG_WRITE(&ctx->hw, CTL_INTF_FLUSH,
> ctx->pending_intf_flush_mask);
>
> - DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask);
> + DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask |
> BIT(DSC_IDX));
> }
>
> static inline void dpu_hw_ctl_trigger_flush(struct dpu_hw_ctl *ctx)
> @@ -507,6 +511,7 @@ static void dpu_hw_ctl_intf_cfg_v1(struct
> dpu_hw_ctl *ctx,
> if (cfg->merge_3d)
> DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE,
> BIT(cfg->merge_3d - MERGE_3D_0));
> + DPU_REG_WRITE(c, CTL_DSC_ACTIVE, BIT(0) | BIT(1) | BIT(2) | BIT(3));
> }
>
> static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,
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