[PATCH 01/27] drm/i915/guc: Fix blocked context accounting

[Daniele Ceraolo Spurio]

On 8/18/2021 11:16 PM, Matthew Brost wrote:
> Prior to this patch the blocked context counter was cleared on
> init_sched_state (used during registering a context & resets) which is
> incorrect. This state needs to be persistent or the counter can read the
> incorrect value resulting in scheduling never getting enabled again.

Can you elaborate a bit more here on the conditions in which we hit this 
issue?
After a GT reset the GuC state is cleared so we need to re-enable 
everything no matter what the old enable status was, so I don't think we 
can hit the described error there, unless your aim is to keep the 
context blocked across the reset (in which case the commit message needs 
rewording). On the registration side, if a context is not registered, it 
will be enabled on the submission that is causing the registration, so 
again we should be covered.

Daniele

> Fixes: 62eaf0ae217d ("drm/i915/guc: Support request cancellation")
> Signed-off-by: Matthew Brost <matthew.brost at intel.com>
> Reviewed-by: Daniel Vetter <daniel.vetter at ffwll.ch>
> Cc: <stable at vger.kernel.org>
> ---
>   drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index 87d8dc8f51b9..69faa39da178 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -152,7 +152,7 @@ static inline void init_sched_state(struct intel_context *ce)
>   {
>   	/* Only should be called from guc_lrc_desc_pin() */
>   	atomic_set(&ce->guc_sched_state_no_lock, 0);
> -	ce->guc_state.sched_state = 0;
> +	ce->guc_state.sched_state &= SCHED_STATE_BLOCKED_MASK;
>   }
>   
>   static inline bool