[PATCH v4 04/16] drm/i915/xehpsdv: Add has_flat_ccs to device info

[Matthew Auld]

On 09/12/2021 15:45, Ramalingam C wrote:
> From: CQ Tang <cq.tang at intel.com>
> 
> Platforms of XeHP and beyond support 3D surface (buffer) compression and
> various compression formats. This is accomplished by an additional
> compression control state (CCS) stored for each surface.
> 
> Gen 12 devices(TGL family and DG1) stores compression states in a separate
> region of memory. It is managed by user-space and has an associated set of
> user-space managed page tables used by hardware for address translation.
> 
> In Xe HP and beyond (XEHPSDV, DG2, etc), there is a new feature introduced
> i.e Flat CCS. It replaced AUX page tables with a flat indexed region of
> device memory for storing compression states.
> 
> Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
> Cc: Matthew Auld <matthew.auld at intel.com>
> Signed-off-by: CQ Tang <cq.tang at intel.com>
> Signed-off-by: Ramalingam C <ramalingam.c at intel.com>
> ---
>   drivers/gpu/drm/i915/i915_drv.h          | 2 ++
>   drivers/gpu/drm/i915/i915_pci.c          | 1 +
>   drivers/gpu/drm/i915/intel_device_info.h | 1 +
>   3 files changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index aeafce112dcd..ad2dd18f7622 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1543,6 +1543,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>   #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
>   #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
>   
> +#define HAS_FLAT_CCS(dev_priv)   (INTEL_INFO(dev_priv)->has_flat_ccs)

Could maybe add a comment here to give brief description of the feature?

Anyway,
Reviewed-by: Matthew Auld <matthew.auld at intel.com>

> +
>   #define HAS_GT_UC(dev_priv)	(INTEL_INFO(dev_priv)->has_gt_uc)
>   
>   #define HAS_POOLED_EU(dev_priv)	(INTEL_INFO(dev_priv)->has_pooled_eu)
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index b523eb1ece5d..382e7278058a 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -1005,6 +1005,7 @@ static const struct intel_device_info adl_p_info = {
>   	XE_HP_PAGE_SIZES, \
>   	.dma_mask_size = 46, \
>   	.has_64bit_reloc = 1, \
> +	.has_flat_ccs = 1, \
>   	.has_global_mocs = 1, \
>   	.has_gt_uc = 1, \
>   	.has_llc = 1, \
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 213ae2c07126..cbbb40e8451f 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -129,6 +129,7 @@ enum intel_ppgtt_type {
>   	func(has_64k_pages); \
>   	func(gpu_reset_clobbers_display); \
>   	func(has_reset_engine); \
> +	func(has_flat_ccs); \
>   	func(has_global_mocs); \
>   	func(has_gt_uc); \
>   	func(has_l3_dpf); \
>