[Intel-gfx] [PATCH 11/14] drm/i915/guc/slpc: Cache platform frequency limits
Belgaumkar, Vinay
vinay.belgaumkar at intel.com
Thu Jul 29 17:24:03 UTC 2021
On 7/29/2021 9:21 AM, Michal Wajdeczko wrote:
>
>
> On 28.07.2021 23:11, Vinay Belgaumkar wrote:
>> Cache rp0, rp1 and rpn platform limits into SLPC structure
>> for range checking while setting min/max frequencies.
>>
>> Also add "soft" limits which keep track of frequency changes
>> made from userland. These are initially set to platform min
>> and max.
>>
>> v2: Address review comments (Michal W)
>> v3: Formatting (Michal W)
>> v4: Add separate function to parse rp values (Michal W)
>> v5: Perform range checking for set min/max (Michal W)
>>
>> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar at intel.com>
>> ---
>> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 115 ++++++++++++++++++
>> .../gpu/drm/i915/gt/uc/intel_guc_slpc_types.h | 9 ++
>> drivers/gpu/drm/i915/i915_reg.h | 3 +
>> 3 files changed, 127 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
>> index 742918875593..bfd5fb0751fd 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
>> @@ -94,6 +94,9 @@ static int slpc_shared_data_init(struct intel_guc_slpc *slpc)
>> return err;
>> }
>>
>> + slpc->max_freq_softlimit = 0;
>> + slpc->min_freq_softlimit = 0;
>
> shouldn't this be in intel_guc_slpc_init() ?
No, we want to maintain softlimits across suspend resume.
>
>> +
>> return err;
>> }
>>
>> @@ -124,6 +127,18 @@ static int guc_action_slpc_set_param(struct intel_guc *guc, u8 id, u32 value)
>> return ret > 0 ? -EPROTO : ret;
>> }
>>
>> +static int guc_action_slpc_unset_param(struct intel_guc *guc, u8 id)
>> +{
>> + u32 request[] = {
>> + GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST,
>> + SLPC_EVENT(SLPC_EVENT_PARAMETER_UNSET, 2),
>> + id,
>> + };
>> +
>> + return intel_guc_send(guc, request, ARRAY_SIZE(request));
>> +}
>> +
>> +
>> static bool slpc_is_running(struct intel_guc_slpc *slpc)
>> {
>> return slpc_get_state(slpc) == SLPC_GLOBAL_STATE_RUNNING;
>> @@ -177,6 +192,16 @@ static int slpc_set_param(struct intel_guc_slpc *slpc, u8 id, u32 value)
>> return ret;
>> }
>>
>> +static int slpc_unset_param(struct intel_guc_slpc *slpc,
>> + u8 id)
>> +{
>> + struct intel_guc *guc = slpc_to_guc(slpc);
>> +
>> + GEM_BUG_ON(id >= SLPC_MAX_PARAM);
>> +
>> + return guc_action_slpc_unset_param(guc, id);
>> +}
>> +
>> static const char *slpc_global_state_to_string(enum slpc_global_state state)
>> {
>> switch (state) {
>> @@ -307,6 +332,11 @@ int intel_guc_slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 val)
>> intel_wakeref_t wakeref;
>> int ret;
>>
>> + if ((val < slpc->min_freq) ||
>> + (val > slpc->rp0_freq) ||
>> + (val < slpc->min_freq_softlimit))
>> + return -EINVAL;
>> +
>> with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
>> ret = slpc_set_param(slpc,
>> SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
>> @@ -317,6 +347,8 @@ int intel_guc_slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 val)
>> ret = -EIO;
>> }
>>
>> + slpc->max_freq_softlimit = val;
>> +
>> return ret;
>> }
>>
>> @@ -363,6 +395,11 @@ int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val)
>> intel_wakeref_t wakeref;
>> int ret;
>>
>> + if ((val < slpc->min_freq) ||
>> + (val > slpc->rp0_freq) ||
>> + (val > slpc->max_freq_softlimit))
>> + return -EINVAL;
>> +
>> with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
>> ret = slpc_set_param(slpc,
>> SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
>> @@ -373,6 +410,8 @@ int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val)
>> ret = -EIO;
>> }
>>
>> + slpc->min_freq_softlimit = val;
>> +
>> return ret;
>> }
>>
>> @@ -418,6 +457,71 @@ void intel_guc_pm_intrmsk_enable(struct intel_gt *gt)
>> GEN6_PMINTRMSK, pm_intrmsk_mbz, 0);
>> }
>>
>> +static int slpc_set_softlimits(struct intel_guc_slpc *slpc)
>> +{
>> + int ret = 0;
>> +
>> + /*
>> + * Softlimits are initially equivalent to platform limits
>> + * unless they have deviated from defaults, in which case,
>> + * we retain the values and set min/max accordingly.
>> + */
>> + if (!slpc->max_freq_softlimit)
>> + slpc->max_freq_softlimit = slpc->rp0_freq;
>> + else if (slpc->max_freq_softlimit != slpc->rp0_freq)
>> + ret = intel_guc_slpc_set_max_freq(slpc,
>> + slpc->max_freq_softlimit);
>
> if this fails, shouldn't we reset max_freq_softlimit to platform limit ?
> otherwise we could be with some potentially bad value forever
Well, if this call fails, it's likely the next set_max_freq call will
also fail, so not much point. Also, it will likely (?) just retain the
old value, which is fine.
>
>> +
>> + if (!slpc->min_freq_softlimit)
>> + slpc->min_freq_softlimit = slpc->min_freq;
>> + else if (slpc->min_freq_softlimit != slpc->min_freq)
>> + ret = intel_guc_slpc_set_min_freq(slpc,
>> + slpc->min_freq_softlimit);
>
> similar here
>
>> +
>> + return ret;
>> +}
>> +
>> +static void intel_guc_slpc_ignore_eff_freq(struct intel_guc_slpc *slpc, bool ignore)
>
> static functions don't need "intel_guc" prefix
>
> slpc_ignore_eff_freq
>
>> +{
>> + /* A failure here does not affect the algorithm in a fatal way */
>> + if (ignore) {
>> + slpc_set_param(slpc,
>> + SLPC_PARAM_IGNORE_EFFICIENT_FREQUENCY,
>> + ignore);
>> + slpc_set_param(slpc,
>> + SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
>> + slpc->min_freq);
>> + } else {
>> + slpc_unset_param(slpc,
>> + SLPC_PARAM_IGNORE_EFFICIENT_FREQUENCY);
>> + slpc_unset_param(slpc,
>> + SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ);
>
> indents are likely wrong
already fixing this and the ones below as part of the checkpatch
warnings I received on this patch set.
Thanks,
Vinay.
>
>> + }
>> +}
>> +
>> +static void intel_guc_slpc_use_fused_rp0(struct intel_guc_slpc *slpc)
>
> slpc_use_fused_rp0
>
>> +{
>> + /* Force SLPC to used platform rp0 */
>> + slpc_set_param(slpc,
>> + SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
>> + slpc->rp0_freq);
>> +}
>> +
>> +static void slpc_get_rp_values(struct intel_guc_slpc *slpc)
>> +{
>> + u32 rp_state_cap;
>> +
>> + rp_state_cap = intel_uncore_read(slpc_to_gt(slpc)->uncore,
>> + GEN6_RP_STATE_CAP);
>> +
>> + slpc->rp0_freq = REG_FIELD_GET(RP0_CAP_MASK, rp_state_cap) *
>> + GT_FREQUENCY_MULTIPLIER;
>> + slpc->rp1_freq = REG_FIELD_GET(RP1_CAP_MASK, rp_state_cap) *
>> + GT_FREQUENCY_MULTIPLIER;
>> + slpc->min_freq = REG_FIELD_GET(RPN_CAP_MASK, rp_state_cap) *
>> + GT_FREQUENCY_MULTIPLIER;
>> +}
>> +
>> /*
>> * intel_guc_slpc_enable() - Start SLPC
>> * @slpc: pointer to intel_guc_slpc.
>> @@ -453,6 +557,17 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
>>
>> intel_guc_pm_intrmsk_enable(&i915->gt);
>>
>> + slpc_get_rp_values(slpc);
>> +
>> + /* Ignore efficient freq and set min/max to platform min/max */
>> + intel_guc_slpc_ignore_eff_freq(slpc, true);
>> + intel_guc_slpc_use_fused_rp0(slpc);
>> +
>> + ret = slpc_set_softlimits(slpc);
>> + if (ret)
>> + drm_err(&i915->drm, "Failed to set SLPC softlimits (%pe)\n",
>> + ERR_PTR(ret));
>
> indent ?
>
>> +
>> return 0;
>> }
>>
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
>> index 3cefe19b17b2..41d13527666f 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
>> @@ -15,6 +15,15 @@ struct intel_guc_slpc {
>> struct slpc_shared_data *vaddr;
>> bool supported;
>> bool selected;
>> +
>> + /* platform frequency limits */
>> + u32 min_freq;
>> + u32 rp0_freq;
>> + u32 rp1_freq;
>> +
>> + /* frequency softlimits */
>> + u32 min_freq_softlimit;
>> + u32 max_freq_softlimit;
>> };
>>
>> #endif
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 5603377e06ca..f3a445f79a36 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -4109,6 +4109,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>> #define BXT_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070)
>> #define GEN6_RP_STATE_LIMITS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)
>> #define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
>> +#define RP0_CAP_MASK REG_GENMASK(7, 0)
>> +#define RP1_CAP_MASK REG_GENMASK(15, 8)
>> +#define RPN_CAP_MASK REG_GENMASK(23, 16)
>> #define BXT_RP_STATE_CAP _MMIO(0x138170)
>> #define GEN9_RP_STATE_LIMITS _MMIO(0x138148)
>>
>>
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