[Intel-gfx] [PATCH 13/14] drm/i915/guc/slpc: Add SLPC selftest
kernel test robot
lkp at intel.com
Fri Jul 30 01:45:53 UTC 2021
Hi Vinay,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-tip/drm-tip]
[cannot apply to drm-intel/for-linux-next drm-exynos/exynos-drm-next tegra-drm/drm/tegra/for-next drm/drm-next v5.14-rc3 next-20210729]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Vinay-Belgaumkar/drm-i915-guc-slpc-Enable-GuC-based-power-management-features/20210729-051427
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: i386-randconfig-c001-20210728 (attached as .config)
compiler: gcc-10 (Ubuntu 10.3.0-1ubuntu1~20.04) 10.3.0
reproduce (this is a W=1 build):
# https://github.com/0day-ci/linux/commit/4567ad693d6988c728447d59050390e308ce6fb0
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Vinay-Belgaumkar/drm-i915-guc-slpc-Enable-GuC-based-power-management-features/20210729-051427
git checkout 4567ad693d6988c728447d59050390e308ce6fb0
# save the attached .config to linux build tree
make W=1 ARCH=i386
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp at intel.com>
All errors (new ones prefixed by >>):
In file included from drivers/gpu/drm/i915/gt/intel_rps.c:2333:
>> drivers/gpu/drm/i915/gt/selftest_slpc.c:37:5: error: no previous prototype for 'live_slpc_clamp_min' [-Werror=missing-prototypes]
37 | int live_slpc_clamp_min(void *arg)
| ^~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gt/selftest_slpc.c:164:5: error: no previous prototype for 'live_slpc_clamp_max' [-Werror=missing-prototypes]
164 | int live_slpc_clamp_max(void *arg)
| ^~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
vim +/live_slpc_clamp_min +37 drivers/gpu/drm/i915/gt/selftest_slpc.c
36
> 37 int live_slpc_clamp_min(void *arg)
38 {
39 struct drm_i915_private *i915 = arg;
40 struct intel_gt *gt = &i915->gt;
41 struct intel_guc_slpc *slpc = >->uc.guc.slpc;
42 struct intel_rps *rps = >->rps;
43 struct intel_engine_cs *engine;
44 enum intel_engine_id id;
45 struct igt_spinner spin;
46 u32 slpc_min_freq, slpc_max_freq;
47 int err = 0;
48
49 if (!intel_uc_uses_guc_slpc(>->uc))
50 return 0;
51
52 if (igt_spinner_init(&spin, gt))
53 return -ENOMEM;
54
55 if (intel_guc_slpc_get_max_freq(slpc, &slpc_max_freq)) {
56 pr_err("Could not get SLPC max freq\n");
57 return -EIO;
58 }
59
60 if (intel_guc_slpc_get_min_freq(slpc, &slpc_min_freq)) {
61 pr_err("Could not get SLPC min freq\n");
62 return -EIO;
63 }
64
65 if (slpc_min_freq == slpc_max_freq) {
66 pr_err("Min/Max are fused to the same value\n");
67 return -EINVAL;
68 }
69
70 intel_gt_pm_wait_for_idle(gt);
71 intel_gt_pm_get(gt);
72 for_each_engine(engine, gt, id) {
73 struct i915_request *rq;
74 u32 step, min_freq, req_freq;
75 u32 act_freq, max_act_freq;
76
77 if (!intel_engine_can_store_dword(engine))
78 continue;
79
80 /* Go from min to max in 5 steps */
81 step = (slpc_max_freq - slpc_min_freq) / NUM_STEPS;
82 max_act_freq = slpc_min_freq;
83 for (min_freq = slpc_min_freq; min_freq < slpc_max_freq;
84 min_freq += step) {
85 err = slpc_set_min_freq(slpc, min_freq);
86 if (err)
87 break;
88
89 st_engine_heartbeat_disable(engine);
90
91 rq = igt_spinner_create_request(&spin,
92 engine->kernel_context,
93 MI_NOOP);
94 if (IS_ERR(rq)) {
95 err = PTR_ERR(rq);
96 st_engine_heartbeat_enable(engine);
97 break;
98 }
99
100 i915_request_add(rq);
101
102 if (!igt_wait_for_spinner(&spin, rq)) {
103 pr_err("%s: Spinner did not start\n",
104 engine->name);
105 igt_spinner_end(&spin);
106 st_engine_heartbeat_enable(engine);
107 intel_gt_set_wedged(engine->gt);
108 err = -EIO;
109 break;
110 }
111
112 /* Wait for GuC to detect business and raise
113 * requested frequency if necessary.
114 */
115 delay_for_h2g();
116
117 req_freq = intel_rps_read_punit_req_frequency(rps);
118
119 /* GuC requests freq in multiples of 50/3 MHz */
120 if (req_freq < (min_freq - 50/3)) {
121 pr_err("SWReq is %d, should be at least %d\n", req_freq,
122 min_freq - 50/3);
123 igt_spinner_end(&spin);
124 st_engine_heartbeat_enable(engine);
125 err = -EINVAL;
126 break;
127 }
128
129 act_freq = intel_rps_read_actual_frequency(rps);
130 if (act_freq > max_act_freq)
131 max_act_freq = act_freq;
132
133 igt_spinner_end(&spin);
134 st_engine_heartbeat_enable(engine);
135 }
136
137 pr_info("Max actual frequency for %s was %d\n",
138 engine->name, max_act_freq);
139
140 /* Actual frequency should rise above min */
141 if (max_act_freq == slpc_min_freq) {
142 pr_err("Actual freq did not rise above min\n");
143 err = -EINVAL;
144 }
145
146 if (err)
147 break;
148 }
149
150 /* Restore min/max frequencies */
151 slpc_set_max_freq(slpc, slpc_max_freq);
152 slpc_set_min_freq(slpc, slpc_min_freq);
153
154 if (igt_flush_test(gt->i915))
155 err = -EIO;
156
157 intel_gt_pm_put(gt);
158 igt_spinner_fini(&spin);
159 intel_gt_pm_wait_for_idle(gt);
160
161 return err;
162 }
163
> 164 int live_slpc_clamp_max(void *arg)
165 {
166 struct drm_i915_private *i915 = arg;
167 struct intel_gt *gt = &i915->gt;
168 struct intel_guc_slpc *slpc;
169 struct intel_rps *rps;
170 struct intel_engine_cs *engine;
171 enum intel_engine_id id;
172 struct igt_spinner spin;
173 int err = 0;
174 u32 slpc_min_freq, slpc_max_freq;
175
176 slpc = >->uc.guc.slpc;
177 rps = >->rps;
178
179 if (!intel_uc_uses_guc_slpc(>->uc))
180 return 0;
181
182 if (igt_spinner_init(&spin, gt))
183 return -ENOMEM;
184
185 if (intel_guc_slpc_get_max_freq(slpc, &slpc_max_freq)) {
186 pr_err("Could not get SLPC max freq\n");
187 return -EIO;
188 }
189
190 if (intel_guc_slpc_get_min_freq(slpc, &slpc_min_freq)) {
191 pr_err("Could not get SLPC min freq\n");
192 return -EIO;
193 }
194
195 if (slpc_min_freq == slpc_max_freq) {
196 pr_err("Min/Max are fused to the same value\n");
197 return -EINVAL;
198 }
199
200 intel_gt_pm_wait_for_idle(gt);
201 intel_gt_pm_get(gt);
202 for_each_engine(engine, gt, id) {
203 struct i915_request *rq;
204 u32 max_freq, req_freq;
205 u32 act_freq, max_act_freq;
206 u32 step;
207
208 if (!intel_engine_can_store_dword(engine))
209 continue;
210
211 /* Go from max to min in 5 steps */
212 step = (slpc_max_freq - slpc_min_freq) / NUM_STEPS;
213 max_act_freq = slpc_min_freq;
214 for (max_freq = slpc_max_freq; max_freq > slpc_min_freq;
215 max_freq -= step) {
216 err = slpc_set_max_freq(slpc, max_freq);
217 if (err)
218 break;
219
220 st_engine_heartbeat_disable(engine);
221
222 rq = igt_spinner_create_request(&spin,
223 engine->kernel_context,
224 MI_NOOP);
225 if (IS_ERR(rq)) {
226 st_engine_heartbeat_enable(engine);
227 err = PTR_ERR(rq);
228 break;
229 }
230
231 i915_request_add(rq);
232
233 if (!igt_wait_for_spinner(&spin, rq)) {
234 pr_err("%s: SLPC spinner did not start\n",
235 engine->name);
236 igt_spinner_end(&spin);
237 st_engine_heartbeat_enable(engine);
238 intel_gt_set_wedged(engine->gt);
239 err = -EIO;
240 break;
241 }
242
243 delay_for_h2g();
244
245 /* Verify that SWREQ indeed was set to specific value */
246 req_freq = intel_rps_read_punit_req_frequency(rps);
247
248 /* GuC requests freq in multiples of 50/3 MHz */
249 if (req_freq > (max_freq + 50/3)) {
250 pr_err("SWReq is %d, should be at most %d\n", req_freq,
251 max_freq + 50/3);
252 igt_spinner_end(&spin);
253 st_engine_heartbeat_enable(engine);
254 err = -EINVAL;
255 break;
256 }
257
258 act_freq = intel_rps_read_actual_frequency(rps);
259 if (act_freq > max_act_freq)
260 max_act_freq = act_freq;
261
262 st_engine_heartbeat_enable(engine);
263 igt_spinner_end(&spin);
264
265 if (err)
266 break;
267 }
268
269 pr_info("Max actual frequency for %s was %d\n",
270 engine->name, max_act_freq);
271
272 /* Actual frequency should rise above min */
273 if (max_act_freq == slpc_min_freq) {
274 pr_err("Actual freq did not rise above min\n");
275 err = -EINVAL;
276 }
277
278 if (igt_flush_test(gt->i915)) {
279 err = -EIO;
280 break;
281 }
282
283 if (err)
284 break;
285 }
286
287 /* Restore min/max freq */
288 slpc_set_max_freq(slpc, slpc_max_freq);
289 slpc_set_min_freq(slpc, slpc_min_freq);
290
291 intel_gt_pm_put(gt);
292 igt_spinner_fini(&spin);
293 intel_gt_pm_wait_for_idle(gt);
294
295 return err;
296 }
297
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
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