[PATCH V7 2/2] drm/bridge: ti-sn65dsi83: Add TI SN65DSI83 and SN65DSI84 driver
kernel test robot
lkp at intel.com
Tue Jun 8 13:41:37 UTC 2021
Hi Marek,
I love your patch! Perhaps something to improve:
[auto build test WARNING on robh/for-next]
[also build test WARNING on drm-intel/for-linux-next drm-exynos/exynos-drm-next tegra-drm/drm/tegra/for-next linus/master v5.13-rc5 next-20210608]
[cannot apply to drm-tip/drm-tip drm/drm-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Marek-Vasut/dt-bindings-drm-bridge-ti-sn65dsi83-Add-TI-SN65DSI83-and-SN65DSI84-bindings/20210608-174220
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: microblaze-randconfig-s031-20210608 (attached as .config)
compiler: microblaze-linux-gcc (GCC) 9.3.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# apt-get install sparse
# sparse version: v0.6.3-341-g8af24329-dirty
# https://github.com/0day-ci/linux/commit/309f2f7d59a0ea5286482ddb0f6a8313317dbb8d
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Marek-Vasut/dt-bindings-drm-bridge-ti-sn65dsi83-Add-TI-SN65DSI83-and-SN65DSI84-bindings/20210608-174220
git checkout 309f2f7d59a0ea5286482ddb0f6a8313317dbb8d
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' W=1 ARCH=microblaze
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp at intel.com>
sparse warnings: (new ones prefixed by >>)
>> drivers/gpu/drm/bridge/ti-sn65dsi83.c:429:13: sparse: sparse: incorrect type in assignment (different base types) @@ expected unsigned short [assigned] [usertype] val @@ got restricted __le16 [usertype] @@
drivers/gpu/drm/bridge/ti-sn65dsi83.c:429:13: sparse: expected unsigned short [assigned] [usertype] val
drivers/gpu/drm/bridge/ti-sn65dsi83.c:429:13: sparse: got restricted __le16 [usertype]
>> drivers/gpu/drm/bridge/ti-sn65dsi83.c:432:13: sparse: sparse: incorrect type in assignment (different base types) @@ expected unsigned short [addressable] [assigned] [usertype] val @@ got restricted __le16 [usertype] @@
drivers/gpu/drm/bridge/ti-sn65dsi83.c:432:13: sparse: expected unsigned short [addressable] [assigned] [usertype] val
drivers/gpu/drm/bridge/ti-sn65dsi83.c:432:13: sparse: got restricted __le16 [usertype]
drivers/gpu/drm/bridge/ti-sn65dsi83.c:436:13: sparse: sparse: incorrect type in assignment (different base types) @@ expected unsigned short [addressable] [assigned] [usertype] val @@ got restricted __le16 [usertype] @@
drivers/gpu/drm/bridge/ti-sn65dsi83.c:436:13: sparse: expected unsigned short [addressable] [assigned] [usertype] val
drivers/gpu/drm/bridge/ti-sn65dsi83.c:436:13: sparse: got restricted __le16 [usertype]
drivers/gpu/drm/bridge/ti-sn65dsi83.c:438:13: sparse: sparse: incorrect type in assignment (different base types) @@ expected unsigned short [addressable] [assigned] [usertype] val @@ got restricted __le16 [usertype] @@
drivers/gpu/drm/bridge/ti-sn65dsi83.c:438:13: sparse: expected unsigned short [addressable] [assigned] [usertype] val
drivers/gpu/drm/bridge/ti-sn65dsi83.c:438:13: sparse: got restricted __le16 [usertype]
drivers/gpu/drm/bridge/ti-sn65dsi83.c:441:13: sparse: sparse: incorrect type in assignment (different base types) @@ expected unsigned short [addressable] [assigned] [usertype] val @@ got restricted __le16 [usertype] @@
drivers/gpu/drm/bridge/ti-sn65dsi83.c:441:13: sparse: expected unsigned short [addressable] [assigned] [usertype] val
drivers/gpu/drm/bridge/ti-sn65dsi83.c:441:13: sparse: got restricted __le16 [usertype]
vim +429 drivers/gpu/drm/bridge/ti-sn65dsi83.c
366
367 static void sn65dsi83_enable(struct drm_bridge *bridge)
368 {
369 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge);
370 unsigned int pval;
371 u16 val;
372 int ret;
373
374 /* Clear reset, disable PLL */
375 regmap_write(ctx->regmap, REG_RC_RESET, 0x00);
376 regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00);
377
378 /* Reference clock derived from DSI link clock. */
379 regmap_write(ctx->regmap, REG_RC_LVDS_PLL,
380 REG_RC_LVDS_PLL_LVDS_CLK_RANGE(sn65dsi83_get_lvds_range(ctx)) |
381 REG_RC_LVDS_PLL_HS_CLK_SRC_DPHY);
382 regmap_write(ctx->regmap, REG_DSI_CLK,
383 REG_DSI_CLK_CHA_DSI_CLK_RANGE(sn65dsi83_get_dsi_range(ctx)));
384 regmap_write(ctx->regmap, REG_RC_DSI_CLK,
385 REG_RC_DSI_CLK_DSI_CLK_DIVIDER(sn65dsi83_get_dsi_div(ctx)));
386
387 /* Set number of DSI lanes and LVDS link config. */
388 regmap_write(ctx->regmap, REG_DSI_LANE,
389 REG_DSI_LANE_DSI_CHANNEL_MODE_SINGLE |
390 REG_DSI_LANE_CHA_DSI_LANES(~(ctx->dsi_lanes - 1)) |
391 /* CHB is DSI85-only, set to default on DSI83/DSI84 */
392 REG_DSI_LANE_CHB_DSI_LANES(3));
393 /* No equalization. */
394 regmap_write(ctx->regmap, REG_DSI_EQ, 0x00);
395
396 /* Set up sync signal polarity. */
397 val = (ctx->mode.flags & DRM_MODE_FLAG_NHSYNC ?
398 REG_LVDS_FMT_HS_NEG_POLARITY : 0) |
399 (ctx->mode.flags & DRM_MODE_FLAG_NVSYNC ?
400 REG_LVDS_FMT_VS_NEG_POLARITY : 0);
401
402 /* Set up bits-per-pixel, 18bpp or 24bpp. */
403 if (ctx->lvds_format_24bpp) {
404 val |= REG_LVDS_FMT_CHA_24BPP_MODE;
405 if (ctx->lvds_dual_link)
406 val |= REG_LVDS_FMT_CHB_24BPP_MODE;
407 }
408
409 /* Set up LVDS format, JEIDA/Format 1 or SPWG/Format 2 */
410 if (ctx->lvds_format_jeida) {
411 val |= REG_LVDS_FMT_CHA_24BPP_FORMAT1;
412 if (ctx->lvds_dual_link)
413 val |= REG_LVDS_FMT_CHB_24BPP_FORMAT1;
414 }
415
416 /* Set up LVDS output config (DSI84,DSI85) */
417 if (!ctx->lvds_dual_link)
418 val |= REG_LVDS_FMT_LVDS_LINK_CFG;
419
420 regmap_write(ctx->regmap, REG_LVDS_FMT, val);
421 regmap_write(ctx->regmap, REG_LVDS_VCOM, 0x05);
422 regmap_write(ctx->regmap, REG_LVDS_LANE,
423 (ctx->lvds_dual_link_even_odd_swap ?
424 REG_LVDS_LANE_EVEN_ODD_SWAP : 0) |
425 REG_LVDS_LANE_CHA_LVDS_TERM |
426 REG_LVDS_LANE_CHB_LVDS_TERM);
427 regmap_write(ctx->regmap, REG_LVDS_CM, 0x00);
428
> 429 val = cpu_to_le16(ctx->mode.hdisplay);
430 regmap_bulk_write(ctx->regmap, REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW,
431 &val, 2);
> 432 val = cpu_to_le16(ctx->mode.vdisplay);
433 regmap_bulk_write(ctx->regmap, REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW,
434 &val, 2);
435 /* 32 + 1 pixel clock to ensure proper operation */
436 val = cpu_to_le16(32 + 1);
437 regmap_bulk_write(ctx->regmap, REG_VID_CHA_SYNC_DELAY_LOW, &val, 2);
438 val = cpu_to_le16(ctx->mode.hsync_end - ctx->mode.hsync_start);
439 regmap_bulk_write(ctx->regmap, REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW,
440 &val, 2);
441 val = cpu_to_le16(ctx->mode.vsync_end - ctx->mode.vsync_start);
442 regmap_bulk_write(ctx->regmap, REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW,
443 &val, 2);
444 regmap_write(ctx->regmap, REG_VID_CHA_HORIZONTAL_BACK_PORCH,
445 ctx->mode.htotal - ctx->mode.hsync_end);
446 regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_BACK_PORCH,
447 ctx->mode.vtotal - ctx->mode.vsync_end);
448 regmap_write(ctx->regmap, REG_VID_CHA_HORIZONTAL_FRONT_PORCH,
449 ctx->mode.hsync_start - ctx->mode.hdisplay);
450 regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_FRONT_PORCH,
451 ctx->mode.vsync_start - ctx->mode.vdisplay);
452 regmap_write(ctx->regmap, REG_VID_CHA_TEST_PATTERN, 0x00);
453
454 /* Enable PLL */
455 regmap_write(ctx->regmap, REG_RC_PLL_EN, REG_RC_PLL_EN_PLL_EN);
456 usleep_range(3000, 4000);
457 ret = regmap_read_poll_timeout(ctx->regmap, REG_RC_LVDS_PLL, pval,
458 pval & REG_RC_LVDS_PLL_PLL_EN_STAT,
459 1000, 100000);
460 if (ret) {
461 dev_err(ctx->dev, "failed to lock PLL, ret=%i\n", ret);
462 /* On failure, disable PLL again and exit. */
463 regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00);
464 return;
465 }
466
467 /* Trigger reset after CSR register update. */
468 regmap_write(ctx->regmap, REG_RC_RESET, REG_RC_RESET_SOFT_RESET);
469
470 /* Clear all errors that got asserted during initialization. */
471 regmap_read(ctx->regmap, REG_IRQ_STAT, &pval);
472 regmap_write(ctx->regmap, REG_IRQ_STAT, pval);
473 }
474
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
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