[PATCH v3 1/2] drm/i915: Use the correct IRQ during resume

[Thomas Zimmermann]

Hi

Am 30.06.21 um 12:49 schrieb Daniel Vetter:
> On Wed, Jun 30, 2021 at 11:52:27AM +0200, Thomas Zimmermann wrote:
>> The code in xcs_resume() probably didn't work as intended. It uses
>> struct drm_device.irq, which is allocated to 0, but never initialized
>> by i915 to the device's interrupt number.
>>
>> v3:
>> 	* also use intel_synchronize_hardirq() at another callsite
>> v2:
>> 	* wrap irq code in intel_synchronize_hardirq() (Ville)
>>
>> Signed-off-by: Thomas Zimmermann <tzimmermann at suse.de>
>> Fixes: 536f77b1caa0 ("drm/i915/gt: Call stop_ring() from ring resume, again")
>> Cc: Chris Wilson <chris at chris-wilson.co.uk>
>> Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com>
>> Cc: Daniel Vetter <daniel.vetter at ffwll.ch>
>> Cc: Rodrigo Vivi <rodrigo.vivi at intel.com>
>> Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
>> Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com>
>> Cc: Lucas De Marchi <lucas.demarchi at intel.com>
>> ---
>>   drivers/gpu/drm/i915/gt/intel_engine_cs.c       | 2 +-
>>   drivers/gpu/drm/i915/gt/intel_ring_submission.c | 2 +-
>>   drivers/gpu/drm/i915/i915_irq.c                 | 5 +++++
>>   drivers/gpu/drm/i915/i915_irq.h                 | 1 +
>>   4 files changed, 8 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> index 88694822716a..5ca3d1664335 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> @@ -1229,7 +1229,7 @@ bool intel_engine_is_idle(struct intel_engine_cs *engine)
>>   		return true;
>>   
>>   	/* Waiting to drain ELSP? */
>> -	synchronize_hardirq(to_pci_dev(engine->i915->drm.dev)->irq);
>> +	intel_synchronize_hardirq(engine->i915);
>>   	intel_engine_flush_submission(engine);
>>   
>>   	/* ELSP is empty, but there are ready requests? E.g. after reset */
>> diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
>> index 5d42a12ef3d6..1b5a22a83db6 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
>> @@ -185,7 +185,7 @@ static int xcs_resume(struct intel_engine_cs *engine)
>>   		     ring->head, ring->tail);
>>   
>>   	/* Double check the ring is empty & disabled before we resume */
>> -	synchronize_hardirq(engine->i915->drm.irq);
>> +	intel_synchronize_hardirq(engine->i915);
>>   	if (!stop_ring(engine))
>>   		goto err;
>>   
>> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>> index 7d0ce8b9f8ed..2203dca19895 100644
>> --- a/drivers/gpu/drm/i915/i915_irq.c
>> +++ b/drivers/gpu/drm/i915/i915_irq.c
>> @@ -4575,3 +4575,8 @@ void intel_synchronize_irq(struct drm_i915_private *i915)
>>   {
>>   	synchronize_irq(to_pci_dev(i915->drm.dev)->irq);
>>   }
>> +
>> +void intel_synchronize_hardirq(struct drm_i915_private *i915)
>> +{
>> +	synchronize_hardirq(to_pci_dev(i915->drm.dev)->irq);
> 
> I honestly think the hardirq here is about as much cargo-culted as using
> the wrong irq number.
> 
> I'd just use intel_synchronize_irq in both places and see whether CI
> complains, then go with that.

Well, ok. I don't think I have Sandybridge HW available. Would the Intel 
CI infrastructure catch any problems with such a change?

Best regards
Thomas

> -Daniel
> 
>> +}
>> diff --git a/drivers/gpu/drm/i915/i915_irq.h b/drivers/gpu/drm/i915/i915_irq.h
>> index db34d5dbe402..e43b6734f21b 100644
>> --- a/drivers/gpu/drm/i915/i915_irq.h
>> +++ b/drivers/gpu/drm/i915/i915_irq.h
>> @@ -94,6 +94,7 @@ void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
>>   void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
>>   bool intel_irqs_enabled(struct drm_i915_private *dev_priv);
>>   void intel_synchronize_irq(struct drm_i915_private *i915);
>> +void intel_synchronize_hardirq(struct drm_i915_private *i915);
>>   
>>   int intel_get_crtc_scanline(struct intel_crtc *crtc);
>>   void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
>> -- 
>> 2.32.0
>>
> 

-- 
Thomas Zimmermann
Graphics Driver Developer
SUSE Software Solutions Germany GmbH
Maxfeldstr. 5, 90409 Nürnberg, Germany
(HRB 36809, AG Nürnberg)
Geschäftsführer: Felix Imendörffer

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