[PATCH v6 05/14] dt-bindings: display: bridge: Add i.MX8qm/qxp display pixel link binding

[Liu Ying]

Hi Marcel,

On Tue, 2021-03-23 at 00:38 +0000, Marcel Ziswiler wrote:
> On Wed, 2021-03-17 at 11:42 +0800, Liu Ying wrote:
> > This patch adds bindings for i.MX8qm/qxp display pixel link.
> > 
> > Reviewed-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A at public.gmane.org>
> > Signed-off-by: Liu Ying <victor.liu-3arQi8VN3Tc at public.gmane.org>
> > ---
> > v5->v6:
> > * No change.
> > 
> > v4->v5:
> > * No change.
> > 
> > v3->v4:
> > * No change.
> > 
> > v2->v3:
> > * Add Rob's R-b tag.
> > 
> > v1->v2:
> > * Use graph schema. (Laurent)
> > * Require all four pixel link output ports. (Laurent)
> > * Mention pixel link is accessed via SCU firmware. (Rob)
> > 
> >  .../display/bridge/fsl,imx8qxp-pixel-link.yaml     | 106 +++++++++++++++++++++
> >  1 file changed, 106 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml
> > 
> > diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml
> > b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml
> > new file mode 100644
> > index 00000000..3af67cc
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml
> > @@ -0,0 +1,106 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.org%2Fschemas%2Fdisplay%2Fbridge%2Ffsl%2Cimx8qxp-pixel-link.yaml%23&data=04%7C01%7Cvictor.liu%40nxp.com%7C281077e1c1324aa89ad008d8ed93f1f0%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637520566973165920%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=2NDRsaWJ6YGFg%2FWAjT1Yf9Y0OaRDSHG0fWghi9UKNRA%3D&reserved=0
> > +$schema: https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.org%2Fmeta-schemas%2Fcore.yaml%23&data=04%7C01%7Cvictor.liu%40nxp.com%7C281077e1c1324aa89ad008d8ed93f1f0%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637520566973165920%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=ogBn2bQmj1YwDqg0KDMXZ%2FwL0VkdOA14n5ayBioMcos%3D&reserved=0
> > +
> > +title: Freescale i.MX8qm/qxp Display Pixel Link
> > +
> > +maintainers:
> > +  - Liu Ying <victor.liu-3arQi8VN3Tc at public.gmane.org>
> > +
> > +description: |
> > +  The Freescale i.MX8qm/qxp Display Pixel Link(DPL) forms a standard
> > +  asynchronous linkage between pixel sources(display controller or
> > +  camera module) and pixel consumers(imaging or displays).
> > +  It consists of two distinct functions, a pixel transfer function and a
> > +  control interface.  Multiple pixel channels can exist per one control channel.
> > +  This binding documentation is only for pixel links whose pixel sources are
> > +  display controllers.
> > +
> > +  The i.MX8qm/qxp Display Pixel Link is accessed via System Controller Unit(SCU)
> > +  firmware.
> > +
> > +properties:
> > +  compatible:
> > +    enum:
> > +      - fsl,imx8qm-dc-pixel-link
> > +      - fsl,imx8qxp-dc-pixel-link
> > +
> > +  ports:
> > +    $ref: /schemas/graph.yaml#/properties/ports
> > +
> > +    properties:
> > +      port at 0:
> > +        $ref: /schemas/graph.yaml#/properties/port
> > +        description: The pixel link input port node from upstream video source.
> > +
> > +    patternProperties:
> > +      "^port@[1-4]$":
> > +        $ref: /schemas/graph.yaml#/properties/port
> > +        description: The pixel link output port node to downstream bridge.
> > +
> > +    required:
> > +      - port at 0
> > +      - port at 1
> > +      - port at 2
> > +      - port at 3
> > +      - port at 4
> > +
> > +required:
> > +  - compatible
> > +  - ports
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    dc0-pixel-link0 {
> > +        compatible = "fsl,imx8qxp-dc-pixel-link";
> > +
> > +        ports {
> > +            #address-cells = <1>;
> > +            #size-cells = <0>;
> > +
> > +            /* from dc0 pixel combiner channel0 */
> > +            port at 0 {
> > +                reg = <0>;
> > +
> > +                dc0_pixel_link0_dc0_pixel_combiner_ch0: endpoint {
> > +                    remote-endpoint = <&dc0_pixel_combiner_ch0_dc0_pixel_link0>;
> > +                };
> > +            };
> > +
> > +            /* to PXL2DPIs in MIPI/LVDS combo subsystems */
> > +            port at 1 {
> > +                #address-cells = <1>;
> > +                #size-cells = <0>;
> > +                reg = <1>;
> > +
> > +                dc0_pixel_link0_mipi_lvds_0_pxl2dpi: endpoint at 0 {
> > +                    reg = <0>;
> > +                    remote-endpoint = <&mipi_lvds_0_pxl2dpi_dc0_pixel_link0>;
> > +                };
> > +
> > +                dc0_pixel_link0_mipi_lvds_1_pxl2dpi: endpoint at 1 {
> > +                    reg = <1>;
> > +                    remote-endpoint = <&mipi_lvds_1_pxl2dpi_dc0_pixel_link0>;
> 
> Those also seem absent from other examples.

Patch 8/14 adds dt-binding for PXL2DPI. An example for the PXL2DPI
instance in 'mipi_lvds_0' subsystem is provided there. It doesn't make
too much sense to provide examples for both 'mipi_lvds_0' subsystem
and 'mipi_lvds_1' subsystem, IMHO. I think it's common that people
usually provide an example for one hardware instance.

Regards,
Liu Ying

> 
> > +                };
> > +            };
> > +
> > +            /* unused */
> > +            port at 2 {
> > +                reg = <2>;
> > +            };
> > +
> > +            /* unused */
> > +            port at 3 {
> > +                reg = <3>;
> > +            };
> > +
> > +            /* to imaging subsystem */
> > +            port at 4 {
> > +                reg = <4>;
> > +            };
> > +        };
> > +    };