[PATCH v1] drm/tegra: dc: Don't set PLL clock to 0Hz

[Thierry Reding]

On Tue, Mar 02, 2021 at 04:15:06PM +0300, Dmitry Osipenko wrote:
> RGB output doesn't allow to change parent clock rate of the display and
> PCLK rate is set to 0Hz in this case. The tegra_dc_commit_state() shall
> not set the display clock to 0Hz since this change propagates to the
> parent clock. The DISP clock is defined as a NODIV clock by the tegra-clk
> driver and all NODIV clocks use the CLK_SET_RATE_PARENT flag.
> 
> This bug stayed unnoticed because by default PLLP is used as the parent
> clock for the display controller and PLLP silently skips the erroneous 0Hz
> rate changes because it always has active child clocks that don't permit
> rate changes. The PLLP isn't acceptable for some devices that we want to
> upstream (like Samsung Galaxy Tab and ASUS TF700T) due to a display panel
> clock rate requirements that can't be fulfilled by using PLLP and then the
> bug pops up in this case since parent clock is set to 0Hz, killing the
> display output.
> 
> Don't touch DC clock if pclk=0 in order to fix the problem.
> 
> Signed-off-by: Dmitry Osipenko <digetx at gmail.com>
> ---
>  drivers/gpu/drm/tegra/dc.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)

Applied, thanks.

Thierry
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