[PATCH 3/3] [RFC] drm/exynos: Add basic i.MX8MM support code

[Tim Harvey]

On Mon, May 10, 2021 at 7:12 AM Adam Ford <aford173 at gmail.com> wrote:
>
> On Mon, Oct 5, 2020 at 8:48 AM Marek Vasut <marex at denx.de> wrote:
> >
> > This adds basic i.MX8MM glue code for the Samsung DSIM PHY.
> > There are still a couple of items which need to be sorted out
> > in drivers/gpu/drm/bridge/samsung-dsim.c before this can even
> > be merged, specifically:
> >
> > - The dsi->out_bridge is not populated until samsung_dsim_host_attach()
> >   is called, however samsung_dsim_host_attach() is not called until the
> >   next bridge attaches and calls mipi_dsi_attach(), and that only happens
> >   after the DSIM calls drm_bridge_attach() on that next bridge.
> >
> > - The samsung_dsim_bridge_mode_fixup() is needed for iMX8MM LCDIF to set
> >   the correct sync flags. This likely needs to be done in the glue code.
>
> Since you asked for an RFC, I
> I applied Michael's series and this series to 5.12 since we are so
> close on having the blk-clk and the power domain stuff working.  I
> also tried your patch for the ti-sn65dsi83 and the adv7511 on the
> Beacon imx8mm development kit.
>
> In both the HDMI bridge and LVDS bridge, I am able to get the modetest
> and drmdevice to return data that looks valid.  The resolution and
> refresh look correct, but I am not able to can an actual image to
> generate out to either the LVDS or the HDMI.  I am able to get the
> image to appear using the NXP kernel with the ADV7511 HDMI bridge, so
> that leads me to believe there might be something wrong with either
> LCDIF or the Samsung DSIM layer code.  I am guess it's the Samsung
> DSIM stuff since the LCDIF has been around for a while.
>
> I am not particularly well versed in the video world, but if you have
> something you'd like me to try, i am willing to try it.
>

Adam,

Try the patches Frieder had to make for his display from his git here:
https://github.com/fschrempf/linux/commits/v5.10-mx8mm-graphics.

I found I needed these for the display I have:
drm/exynos: Fix DE polarity for usage with LCDIF encoder
drm/exynos: Fix PLL PMS offset for P value bitfield

Best regards,

Tim