[PATCH V2] dt-bindings: display: Fix spacing in lvds.yaml

[Laurent Pinchart]

Hi Marek,

Thank you for the patch.

On Tue, May 18, 2021 at 12:43:36AM +0200, Marek Vasut wrote:
> Add missing spaces to make the diagrams readable, no functional change.
> 
> Signed-off-by: Marek Vasut <marex at denx.de>
> Cc: Laurent Pinchart <laurent.pinchart at ideasonboard.com>
> Cc: Rob Herring <robh+dt at kernel.org>
> Cc: Sam Ravnborg <sam at ravnborg.org>
> Cc: devicetree at vger.kernel.org
> To: dri-devel at lists.freedesktop.org
> ---
> V2: Replace all the other tabs too

Thanks for taking my comment into account.

Reviewed-by: Laurent Pinchart <laurent.pinchart at ideasonboard.com>

> ---
>  .../bindings/display/panel/lvds.yaml          | 46 +++++++++----------
>  1 file changed, 23 insertions(+), 23 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/display/panel/lvds.yaml b/Documentation/devicetree/bindings/display/panel/lvds.yaml
> index 31164608ba1d..49460c9dceea 100644
> --- a/Documentation/devicetree/bindings/display/panel/lvds.yaml
> +++ b/Documentation/devicetree/bindings/display/panel/lvds.yaml
> @@ -51,37 +51,37 @@ properties:
>        - "jeida-18" - 18-bit data mapping compatible with the [JEIDA], [LDI] and
>          [VESA] specifications. Data are transferred as follows on 3 LVDS lanes.
>  
> -      Slot	    0       1       2       3       4       5       6
> -            ________________                         _________________
> -      Clock	                \_______________________/
> -              ______  ______  ______  ______  ______  ______  ______
> -      DATA0	><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
> -      DATA1	><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
> -      DATA2	><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
> +      Slot          0       1       2       3       4       5       6
> +                ________________                         _________________
> +      Clock                     \_______________________/
> +                  ______  ______  ______  ______  ______  ______  ______
> +      DATA0     ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
> +      DATA1     ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
> +      DATA2     ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
>  
>        - "jeida-24" - 24-bit data mapping compatible with the [DSIM] and [LDI]
>          specifications. Data are transferred as follows on 4 LVDS lanes.
>  
> -      Slot	    0       1       2       3       4       5       6
> -            ________________                         _________________
> -      Clock	                \_______________________/
> -              ______  ______  ______  ______  ______  ______  ______
> -      DATA0	><__G2__><__R7__><__R6__><__R5__><__R4__><__R3__><__R2__><
> -      DATA1	><__B3__><__B2__><__G7__><__G6__><__G5__><__G4__><__G3__><
> -      DATA2	><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__><
> -      DATA3	><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__><
> +      Slot          0       1       2       3       4       5       6
> +                ________________                         _________________
> +      Clock                     \_______________________/
> +                  ______  ______  ______  ______  ______  ______  ______
> +      DATA0     ><__G2__><__R7__><__R6__><__R5__><__R4__><__R3__><__R2__><
> +      DATA1     ><__B3__><__B2__><__G7__><__G6__><__G5__><__G4__><__G3__><
> +      DATA2     ><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__><
> +      DATA3     ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__><
>  
>        - "vesa-24" - 24-bit data mapping compatible with the [VESA] specification.
>          Data are transferred as follows on 4 LVDS lanes.
>  
> -      Slot	    0       1       2       3       4       5       6
> -            ________________                         _________________
> -      Clock	                \_______________________/
> -              ______  ______  ______  ______  ______  ______  ______
> -      DATA0	><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
> -      DATA1	><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
> -      DATA2	><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
> -      DATA3	><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__><
> +      Slot          0       1       2       3       4       5       6
> +                ________________                         _________________
> +      Clock                     \_______________________/
> +                  ______  ______  ______  ______  ______  ______  ______
> +      DATA0     ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
> +      DATA1     ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
> +      DATA2     ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
> +      DATA3     ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__><
>  
>        Control signals are mapped as follows.
>  

-- 
Regards,

Laurent Pinchart