[RFC PATCH v2 2/3] arm64: dts: imx8mm: Add MIPI DSI pipeline

[Jagan Teki]

On Thu, Nov 11, 2021 at 3:51 PM Marek Vasut <marex at denx.de> wrote:
>
> On 11/11/21 11:14 AM, Jagan Teki wrote:
>
> [...]
>
> > +                     dsi: dsi at 32e10000 {
> > +                             compatible = "fsl,imx8mm-mipi-dsim";
> > +                             reg = <0x32e10000 0x400>;
> > +                             clocks = <&clk IMX8MM_CLK_DSI_CORE>,
> > +                                      <&clk IMX8MM_CLK_DSI_PHY_REF>;
> > +                             clock-names = "bus_clk", "sclk_mipi";
> > +                             assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>,
> > +                                               <&clk IMX8MM_VIDEO_PLL1_OUT>,
> > +                                               <&clk IMX8MM_CLK_DSI_PHY_REF>;
> > +                             assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
> > +                                                      <&clk IMX8MM_VIDEO_PLL1_BYPASS>,
> > +                                                      <&clk IMX8MM_VIDEO_PLL1_OUT>;
> > +                             assigned-clock-rates = <266000000>, <594000000>, <27000000>;
> > +                             interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> > +                             phys = <&mipi_phy 0>;
> > +                             phy-names = "dsim";
> > +                             power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_DSI>;
> > +                             samsung,burst-clock-frequency = <891000000>;
> > +                             samsung,esc-clock-frequency = <54000000>;
> > +                             samsung,pll-clock-frequency = <27000000>;
> > +                             status = "disabled";
>
>
> This 27 MHz is really IMX8MM_CLK_DSI_PHY_REF and
> samsung,burst-clock-frequency is really the DSI link clock which is
> panel/bridge specific ... but, why do we need to specify such policy in
> DT rather than have the panel/bridge drivers negotiate the best clock
> settings with DSIM bridge driver ? This should be something which should
> be implemented in the DRM subsystem, not hard-coded in DT. These ad-hoc
> samsung,*-clock-frequency properties shouldn't even be needed then.

This look confusion for me, all three clock are used it directly from
exynos. and these indeed are computing pll for this bridge and clock
control of dsim registers are updated from this out come values. No
thoughts as of now how to handle these externally and update the
internal register based on those out come values.

>
> Also, are the DSIM bindings stable now ?

Issue still lies on exynos dsi side, the final driver is not binding
properly. I'm trying to send the next version patches only for
existing exynos dsi to convert into bridge. and subsequently adding
i.mx8mm specifics. More problem for me to test it on exynos boards, i
don't have any either.

Jagan.