Exynos DSI bridge conversion

[Jagan Teki]

Hi Andrej and all,

I'm trying to convert existing exynos dsi driver to bridge and make
them accessible for i.MX8MM platform.

I've a few questions on the existing exynos dsi driver and which is
indeed incompatible to proceed to make the bridge conversion.

1. Hotplug event

Commit from 295e7954c0d3fdbe0550d13e3cf4dd4604d42c68 which is waiting
for drm to hotplug the downstream devices like panel or bridge to
probe.

Any idea how it works? what if we move drm_bridge_attach in bind
callback so-that binding will start once all the devices get attached.

2. Host register in bind

Usual host registration is done in the probe, but the driver registers
host in bind once the in_bridge is attached. any idea why? What if we
find the DSI as an output port in MIC and start attaching from there?

3. CRTC handling in DSI

Commit from c038f53842cf840889473d219ace7f9121694e8d is trying to send
the DSI flags information to CRTC with a function call. any specific
reason for this? Any proper way of doing this move out from DSI?

4. Mutex calls while assigning device attributes.

Assignment of lanes, format, mode_flags are done in mutex context, I
think we can even do it in normal context isn't it? or any specific
reason for doing this?

5. Clock rates.

pll_clk_rate, burst_clk_rate, burst_clk_rate are these clock rates
retrieved from DT. which is not a proper way to support multi
platform. I think pll-clock and burst-clock are computed based on
panel pixel or bridge clocks. any specific computation for these to
handle dynamically on code?

All this information is essential for me to move this further as I
don't have direct hardware and I'm trying to take some help from Marek
Szyprowski.

Please take some time, and help me.

Thanks,
Jagan.