[bug report] drm/msm: Add SDM845 DPU support

[Dan Carpenter]

Hello Jeykumar Sankaran,

The patch 25fdd5933e4c: "drm/msm: Add SDM845 DPU support" from Jun
27, 2018, leads to the following
Smatch static checker warning:

	drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c:359 dpu_encoder_phys_cmd_tearcheck_config()
	warn: 'vsync_hz' unsigned <= 0

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
    322 static void dpu_encoder_phys_cmd_tearcheck_config(
    323                 struct dpu_encoder_phys *phys_enc)
    324 {
    325         struct dpu_encoder_phys_cmd *cmd_enc =
    326                 to_dpu_encoder_phys_cmd(phys_enc);
    327         struct dpu_hw_tear_check tc_cfg = { 0 };
    328         struct drm_display_mode *mode;
    329         bool tc_enable = true;
    330         u32 vsync_hz;
                ^^^^^^^^^^^^

    331         struct dpu_kms *dpu_kms;
    332 
    333         if (!phys_enc->hw_pp) {
    334                 DPU_ERROR("invalid encoder\n");
    335                 return;
    336         }
    337         mode = &phys_enc->cached_mode;
    338 
    339         DPU_DEBUG_CMDENC(cmd_enc, "pp %d\n", phys_enc->hw_pp->idx - PINGPONG_0);
    340 
    341         if (!phys_enc->hw_pp->ops.setup_tearcheck ||
    342                 !phys_enc->hw_pp->ops.enable_tearcheck) {
    343                 DPU_DEBUG_CMDENC(cmd_enc, "tearcheck not supported\n");
    344                 return;
    345         }
    346 
    347         dpu_kms = phys_enc->dpu_kms;
    348 
    349         /*
    350          * TE default: dsi byte clock calculated base on 70 fps;
    351          * around 14 ms to complete a kickoff cycle if te disabled;
    352          * vclk_line base on 60 fps; write is faster than read;
    353          * init == start == rdptr;
    354          *
    355          * vsync_count is ratio of MDP VSYNC clock frequency to LCD panel
    356          * frequency divided by the no. of rows (lines) in the LCDpanel.
    357          */
    358         vsync_hz = dpu_kms_get_clk_rate(dpu_kms, "vsync");
--> 359         if (vsync_hz <= 0) {

dpu_kms_get_clk_rate() returns -EINVAL (but cast to u64).  The "vsync_hz"
variable is a u32 so it can't be less than zero and the -EINVAL is
treated as a success.

    360                 DPU_DEBUG_CMDENC(cmd_enc, "invalid - vsync_hz %u\n",
    361                                  vsync_hz);
    362                 return;
    363         }
    364 
    365         tc_cfg.vsync_count = vsync_hz /
    366                                 (mode->vtotal * drm_mode_vrefresh(mode));

regards,
dan carpenter

regards,
dan carpenter