DSI Bridge switching

[Jagan Teki]

Hi Dave,

On Fri, Oct 8, 2021 at 9:32 PM Dave Stevenson
<dave.stevenson at raspberrypi.com> wrote:
>
> On Fri, 8 Oct 2021 at 14:37, Laurent Pinchart
> <laurent.pinchart at ideasonboard.com> wrote:
> >
> > Hello,
> >
> > On Fri, Oct 08, 2021 at 03:27:43PM +0200, Andrzej Hajda wrote:
> > > Hi,
> > >
> > > Removed my invalid email (I will update files next week).
> > >
> > > On 08.10.2021 13:14, Jagan Teki wrote:
> > > > Hi,
> > > >
> > > > I think this seems to be a known use case for industrial these days with i.mx8m.
> > > >
> > > > The host DSI would configure with two bridges one for DSI to LVDS
> > > > (SN65DSI83) and another for DSI to HDMI Out (ADV7535). Technically we
> > > > can use only one bridge at a time as host DSI support single out port.
> > > > So we can have two separate device tree files for LVDS and HDMI and
> > > > load them static.
> > > >
> > > > But, one of the use cases is to support both of them in single dts, and
> > > > - Turn On LVDS (default)
> > > > - Turn Off LVDS then Turn On HDMI when cable plug-in
> > >
> > > Are you sure it will work from hardware PoV? Do you have some demuxer?
> > > isolation of pins?
> >
> > It may be in the category of "you shouldn't do this, but it actually
> > works". I've seen the same being done with two CSI-2 camera sensors
> > connected to the same receiver, with one of them being held in reset at
> > all times.
>
> Surely the correct way to do this would be with a D-PHY mux chip such
> as OnSemi FSA642 [1] or those from Diodes Incorporated [2].
> How you'd integrate such a mux into DRM is a totally different question.
> With V4L2 and CSI2 it'd be relatively simple via Media Controller.
>
> Just wiring them together isn't going to work very well for DSI
> reverse direction communication, but neither of the chips Jagan lists
> support this.

Sorry to mention it before, we have two 2:1 MIPI D-PHY Switch [1] on
the design which take 2 data-lanes and clock from Host and produce 4
data-lane and 1 clock to connect to ADV7535 and SN65DSI84 bridges. The
switch has OE, SEL pins to select the desired to MUXed lanes/clock
routing to an appropriate bridge.

I think supporting the switch in the pipeline or logic that handle the
bridge switching might help.

[1] https://www.diodes.com/assets/Datasheets/PI3WVR626.pdf

Jagan.