[PATCH v2 07/11] drm/msm/disp/dpu1: Add DSC support in hw_ctl

[Vinod Koul]

On 14-10-21, 17:06, Dmitry Baryshkov wrote:
> On 07/10/2021 10:08, Vinod Koul wrote:
> > Later gens of hardware have DSC bits moved to hw_ctl, so configure these
> > bits so that DSC would work there as well
> > 
> > Signed-off-by: Vinod Koul <vkoul at kernel.org>
> > ---
> > Changes since
> > v1:
> >   - Move this patch from 6 to 7 due to dependency on 6th one
> >   - Use DSC indices for programming DSC registers and program only on non
> >     null indices
> > 
> >   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 12 ++++++++++--
> >   1 file changed, 10 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> > index 3c79bd9c2fe5..8ea9d8dce3f7 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> > @@ -25,6 +25,8 @@
> >   #define   CTL_MERGE_3D_ACTIVE           0x0E4
> >   #define   CTL_INTF_ACTIVE               0x0F4
> >   #define   CTL_MERGE_3D_FLUSH            0x100
> > +#define   CTL_DSC_ACTIVE                0x0E8
> > +#define   CTL_DSC_FLUSH                0x104
> >   #define   CTL_INTF_FLUSH                0x110
> >   #define   CTL_INTF_MASTER               0x134
> >   #define   CTL_FETCH_PIPE_ACTIVE         0x0FC
> > @@ -34,6 +36,7 @@
> >   #define DPU_REG_RESET_TIMEOUT_US        2000
> >   #define  MERGE_3D_IDX   23
> > +#define  DSC_IDX        22
> >   #define  INTF_IDX       31
> >   #define CTL_INVALID_BIT                 0xffff
> > @@ -120,7 +123,6 @@ static u32 dpu_hw_ctl_get_pending_flush(struct dpu_hw_ctl *ctx)
> >   static void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx)
> >   {
> > -
> >   	if (ctx->pending_flush_mask & BIT(MERGE_3D_IDX))
> >   		DPU_REG_WRITE(&ctx->hw, CTL_MERGE_3D_FLUSH,
> >   				ctx->pending_merge_3d_flush_mask);
> > @@ -128,7 +130,6 @@ static void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx)
> >   		DPU_REG_WRITE(&ctx->hw, CTL_INTF_FLUSH,
> >   				ctx->pending_intf_flush_mask);
> > -	DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask);
> 
> This would break non-DSC case.

This is a mistake, I have fixed it up now..

> >   }
> >   static inline void dpu_hw_ctl_trigger_flush(struct dpu_hw_ctl *ctx)
> > @@ -498,6 +499,9 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
> >   	u32 intf_active = 0;
> >   	u32 mode_sel = 0;
> > +	if (cfg->dsc)
> > +		DPU_REG_WRITE(&ctx->hw, CTL_DSC_FLUSH, cfg->dsc);
> > +
> >   	if (cfg->intf_mode_sel == DPU_CTL_MODE_SEL_CMD)
> >   		mode_sel |= BIT(17);
> > @@ -509,6 +513,10 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
> >   	if (cfg->merge_3d)
> >   		DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE,
> >   			      BIT(cfg->merge_3d - MERGE_3D_0));
> > +	if (cfg->dsc) {
> > +		DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask |  BIT(DSC_IDX));
> 
> Why?

I have fixed it up to write only DSC_IDX

-- 
~Vinod