[PATCH v3 08/10] drm/i915/xehp: Make IRQ reset and postinstall multi-tile aware
Matt Roper
matthew.d.roper at intel.com
Fri Oct 29 03:28:15 UTC 2021
From: Paulo Zanoni <paulo.r.zanoni at intel.com>
Loop through all the tiles when initializing and resetting interrupts.
v2:
- Access tile0 registers through dev_priv->uncore rather than
dev_priv->gt.uncore for clarity.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
Reviewed-by: Andi Shyti <andi.shyti at linux.intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 28 ++++++++++++++++++----------
1 file changed, 18 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 57a58151eaae..c2955916e0fe 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3194,14 +3194,19 @@ static void dg1_irq_reset(struct drm_i915_private *dev_priv)
{
struct intel_gt *gt = &dev_priv->gt;
struct intel_uncore *uncore = gt->uncore;
+ unsigned int i;
dg1_master_intr_disable(dev_priv->uncore.regs);
- gen11_gt_irq_reset(gt);
- gen11_display_irq_reset(dev_priv);
+ for_each_gt(dev_priv, i, gt) {
+ gen11_gt_irq_reset(gt);
- GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
- GEN3_IRQ_RESET(uncore, GEN8_PCU_);
+ uncore = gt->uncore;
+ GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
+ GEN3_IRQ_RESET(uncore, GEN8_PCU_);
+ }
+
+ gen11_display_irq_reset(dev_priv);
}
void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
@@ -3894,13 +3899,16 @@ static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
{
- struct intel_gt *gt = &dev_priv->gt;
- struct intel_uncore *uncore = gt->uncore;
+ struct intel_gt *gt;
u32 gu_misc_masked = GEN11_GU_MISC_GSE;
+ unsigned int i;
- gen11_gt_irq_postinstall(gt);
+ for_each_gt(dev_priv, i, gt) {
+ gen11_gt_irq_postinstall(gt);
- GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
+ GEN3_IRQ_INIT(gt->uncore, GEN11_GU_MISC_, ~gu_misc_masked,
+ gu_misc_masked);
+ }
if (HAS_DISPLAY(dev_priv)) {
icp_irq_postinstall(dev_priv);
@@ -3909,8 +3917,8 @@ static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
GEN11_DISPLAY_IRQ_ENABLE);
}
- dg1_master_intr_enable(uncore->regs);
- intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR);
+ dg1_master_intr_enable(dev_priv->uncore.regs);
+ intel_uncore_posting_read(&dev_priv->uncore, DG1_MSTR_TILE_INTR);
}
static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
--
2.33.0
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