[PATCH] drm/bridge: ti-sn65dsi83: Check link status register after enabling the bridge

Wed Sep 8 11:11:11 UTC 2021

Hi Marek and Andrzej

On Tue, 7 Sept 2021 at 22:24, Marek Vasut <marex at denx.de> wrote:
>
> On 9/7/21 7:29 PM, Andrzej Hajda wrote:
> >
> > W dniu 07.09.2021 o 16:25, Marek Vasut pisze:
> >> On 9/7/21 9:31 AM, Andrzej Hajda wrote:
> >>> On 07.09.2021 04:39, Marek Vasut wrote:
> >>>> In rare cases, the bridge may not start up correctly, which usually
> >>>> leads to no display output. In case this happens, warn about it in
> >>>> the kernel log.
> >>>>
> >>>> Signed-off-by: Marek Vasut <marex at denx.de>
> >>>> Cc: Jagan Teki <jagan at amarulasolutions.com>
> >>>> Cc: Laurent Pinchart <laurent.pinchart at ideasonboard.com>
> >>>> Cc: Linus Walleij <linus.walleij at linaro.org>
> >>>> Cc: Robert Foss <robert.foss at linaro.org>
> >>>> Cc: Sam Ravnborg <sam at ravnborg.org>
> >>>> Cc: dri-devel at lists.freedesktop.org
> >>>> ---
> >>>> NOTE: See the following:
> >>>> https://e2e.ti.com/support/interface-group/interface/f/interface-forum/942005/sn65dsi83-dsi83-lvds-bridge---sporadic-behavior---no-video
> >>>>
> >>>> https://community.nxp.com/t5/i-MX-Processors/i-MX8M-MIPI-DSI-Interface-LVDS-Bridge-Initialization/td-p/1156533
> >>>>
> >>>> ---
> >>>>     drivers/gpu/drm/bridge/ti-sn65dsi83.c | 5 +++++
> >>>>     1 file changed, 5 insertions(+)
> >>>>
> >>>> diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi83.c
> >>>> b/drivers/gpu/drm/bridge/ti-sn65dsi83.c
> >>>> index a32f70bc68ea4..4ea71d7f0bfbc 100644
> >>>> --- a/drivers/gpu/drm/bridge/ti-sn65dsi83.c
> >>>> +++ b/drivers/gpu/drm/bridge/ti-sn65dsi83.c
> >>>> @@ -520,6 +520,11 @@ static void sn65dsi83_atomic_enable(struct
> >>>> drm_bridge *bridge,
> >>>>         /* Clear all errors that got asserted during initialization. */
> >>>>         regmap_read(ctx->regmap, REG_IRQ_STAT, &pval);
> >>>>         regmap_write(ctx->regmap, REG_IRQ_STAT, pval);
> >>>
> >>>
> >>> It does not look as correct error handling, maybe it would be good to
> >>> analyze and optionally report 'unexpected' errors here as well.
> >>
> >> The above is correct -- it clears the status register because the
> >> setup might've set random bits in that register. Then we wait a bit,
> >> let the link run, and read them again to get the real link status in
> >> this new piece of code below, hence the usleep_range there. And then
> >> if the link indicates a problem, we know it is a problem.
> >
> >
> > Usually such registers are cleared on very beginning of the
> > initialization, and tested (via irq handler, or via reading), during
> > initalization, if initialization phase goes well. If it is not the case
> > forgive me.
>
> The init just flips the bit at random in the IRQ_STAT register, so no,
> that's not really viable here. That's why we clear them at the end, and
> then wait a bit, and then check whether something new appeared in them.
>
> If not, all is great.
>
> Sure, we could generate an IRQ, but then IRQ line is not always
> connected to this chip on all hardware I have available. So this gives
> the user at least some indication that something is wrong with their HW.
>
> >>>> +
> >>>> +    usleep_range(10000, 12000);
> >>>> +    regmap_read(ctx->regmap, REG_IRQ_STAT, &pval);
> >>>> +    if (pval)
> >>>> +        dev_err(ctx->dev, "Unexpected link status 0x%02x\n", pval);
> >>>
> >>>
> >>> I am not sure what is the case here but it looks like 'we do not know
> >>> what is going on, so let's add some diagnostic messages to gather info
> >>> and figure it out later'.
> >>
> >> That's pretty much the case, see the two links above in the NOTE
> >> section. If something goes wrong, we print the value for the user
> >> (usually developer) so they can fix their problems. We cannot do much
> >> better in the attach callback.
> >>
> >> The issue I ran into (and where this would be helpful information to
> >> me during debugging, since the issue happened real seldom, see also
> >> the NOTE links above) is that the DSI controller driver started
> >> streaming video on the data lanes before the DSI83 had a chance to
> >> initialize. This worked most of the time, except for a few exceptions
> >> here and there, where the video didn't start. This does set link
> >> status bits consistently. In the meantime, I fixed the controller
> >> driver (so far downstream, due to ongoing discussion).
> >
> >
> > Maybe drm_connector_set_link_status_property(conn,
> > DRM_MODE_LINK_STATUS_BAD) would be usefule here.
>
> Hmm, this works on connector, the dsi83 is a bridge and it can be stuck
> between two other bridges. That doesn't seem like the right tool, no ?
>
> >>> Whole driver lacks IRQ handler which IMO could perform better diagnosis,
> >>> and I guess it could also help in recovery, but this is just my guess.
> >>> So if this patch is enough for now you can add:
> >>
> >> No, IRQ won't help you here, because by the time you get the IRQ, the
> >> DSI host already started streaming video on data lanes and you won't
> >> be able to correctly reinit the DSI83 unless you communicate to the
> >> DSI host that it should switch the data lanes back to LP11.
> >>
> >> And for that, there is a bigger chunk missing really. What needs to be
> >> added is a way for the DSI bridge / panel to communicate its needs to
> >> the DSI host -- things like "I need DSI clock lane frequency f MHz, I
> >> need clock lane in HS mode and data lanes in LP11 mode". If you look
> >> at the way DSI hosts and bridges/panels work out the DSI link
> >> parameters, you will notice they basically do it each on their own,
> >> there is no such API or communication channel.
> >
> >
> > There is one-time communication channel via mipi_dsi_attach, it allows
> > to set max frequency i HS and LP, choose mode of operation (HS/LPM) and
> > few more things. If it is necessary to extend it please propse sth.
>
> Well, take for example the drivers/gpu/drm/exynos/exynos_drm_dsi.c ,
> there is this:
>
> static void exynos_dsi_enable(struct drm_encoder *encoder)
> ...
>                  list_for_each_entry_reverse(iter, &dsi->bridge_chain,
>                                              chain_node) {
>                          if (iter->funcs->pre_enable)
>                                  iter->funcs->pre_enable(iter);
> ...
>          exynos_dsi_set_display_mode(dsi);
>          exynos_dsi_set_display_enable(dsi, true);
> ...
>                  list_for_each_entry(iter, &dsi->bridge_chain, chain_node) {
>                          if (iter->funcs->enable)
>                                  iter->funcs->enable(iter);
>                  }
> ...
>
> So the bridge enable callback is called with clock lane already in HS
> mode, and data lanes streaming video. This doesn't work with the DSI83,
> which would need clock lane in HS and providing clock , but data lanes
> in LP11 with no video.
>
> Sure, I could probably move exynos_dsi_set_display_enable(dsi, true);
> after the enable call, but is that really the right solution ? What
> about bridges which need some other specific configuration of the data
> lanes during init ?

I hadn't noticed that Exynos was doing that.
vc4 DSI is doing the same thing in deliberately breaking the
panel/bridge chain so that it gets a chance to do some initialisation
before panel/bridge pre_enable.

Another issue I've noted in doing this is that it breaks calls to the
bridge's mode_set, mode_valid, and mode_fixup hooks. The framework
doesn't know about the bridges/panels beyond the encoder, and the
encoder doesn't get all the information required in order to replicate
those calls.
I'm about to look into whether switching the DSI host to being a
bridge instead of an encoder allows me to overcome that one.
Doing so doesn't solve the issue of the DSI host bridge pre_enable
being called after the panel/bridge pre_enable though.

> > Regarding requesting LP11 I am not sure if we really should have such
> > low level communication. LP11, as I remember ,is initial state in HS so
> > it should be set anyway, before starting video transmission.

LP-11 is the idle LP state. Both P and N lines of the pair are at
LP-high (~1.2V).
You then have an escape sequence to shift to HS mode (LP-01 for
T(lpx), LP-00 for T(hs-prepare), enable HS driver) when you are
wishing to send data bursts. The signalling levels for HS drop to
~100mV for low and ~300mV for high.

Add in ULPS which is effectively powered off but has a specific entry
and escape sequence to sleep/wake up the receiving device. ULPS seems
to be totally ignored in DRM as it seems to rely on regulator or other
control of the panel/bridge to power down.

> Well, see above, that's the problem I ran across recently.
>
> > And maybe this is the main problem:
> >
> > DRM core calls:
> >
> > crtc->enable
> >
> > bridges->pre_enable,
> >
> > encoder->enable,
> >
> > bridges->enable.
> >
> >
> > Usually video transmission starts in crtc->enable (CRTC->Encoder), and
> > in encoder->enable (encoder->bridge), so in bridges->enable it would be
> > too late for LP11 state - transmission can be already in progress.
> >
> > It shows well that this order of calls does not fit well to DSI, and
> > probably many other protocols.
> >
> > Maybe moving most of the bridge->enable code to bridge->pre_enable would
> > help, but I am not sur if it will not pose another issues.
>
> Yep, that won't work e.g. with the exynos DSIM, because
> exynos_dsi_set_display_mode() sets the data lanes to LP11.

Isn't the bigger question for SN65DSI8[3|4|5] whether the clock lane
is running or not in pre_enable?

> > This is quick analysis, so please fix me if I am wrong.
>
> I pretty much agree that the current state of things does not fit with
> DSI too well.

That was why I was questioning how DSI was meant to be implemented in
https://lore.kernel.org/dri-devel/CAPY8ntBUKRkSam59Y+72dW_6XOeKVswPWffzPj3uvgE6pV4ZGQ@mail.gmail.com/

The need to have the DSI host in a defined idle state (often LP-11,
but varying whether the clock lane is in HS) before powering up the
panel/bridge is incredibly common, but currently undefined in DRM.

Taking the SN65DSI83 as an example, the datasheet [1] section 7.4.2
states that the clock lane must be in HS mode, and data lanes in LP-11
when coming out of reset. That means that we can't be "enable" as that
will have the data lanes in HS mode and sending video, and as we can't
be in "pre_enable" as the DSI PHY will be powered down and so we won't
have the clock lanes in HS mode.

I've hit a similar one with the Toshiba TC358762 where it seems to get
upset if it is receiving video data when it gets configured.
panel-raspberrypi-touchscreen[2] which drives that chip is
intermittent when using panel enable, whereas panel prepare is
significantly more reliable but relies on the DSI host being
initialised to LP-11 by breaking the chain.

  Dave

[1] https://www.ti.com/lit/ds/symlink/sn65dsi83.pdf
[2] https://github.com/torvalds/linux/blob/master/drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c