[Freedreno] [PATCH] drm/msm/dsi/phy: fix clock names in 28nm_8960 phy

[abhinavk at codeaurora.org]

On 2021-09-21 09:22, Dmitry Baryshkov wrote:
> The commit 9f91f22aafcd ("drm/msm/dsi: remove duplicate fields from
> dsi_pll_Nnm instances") mistakenly changed registered clock names. 
> While
> the platform is in progress of migration to using clock properties in
> the dts rather than the global clock names, we should provide backwards
> compatibility. Thus restore registerd global clock names.
> 
> Fixes: 9f91f22aafcd ("drm/msm/dsi: remove duplicate fields from
> dsi_pll_Nnm instances")
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov at linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk at codeaurora.org>
> ---
>  drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
> index aaa37456f4ee..71ed4aa0dc67 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
> @@ -428,7 +428,7 @@ static int pll_28nm_register(struct dsi_pll_28nm
> *pll_28nm, struct clk_hw **prov
>  	bytediv->reg = pll_28nm->phy->pll_base + 
> REG_DSI_28nm_8960_PHY_PLL_CTRL_9;
> 
>  	snprintf(parent_name, 32, "dsi%dvco_clk", pll_28nm->phy->id);
> -	snprintf(clk_name, 32, "dsi%dpllbyte", pll_28nm->phy->id);
> +	snprintf(clk_name, 32, "dsi%dpllbyte", pll_28nm->phy->id + 1);
> 
>  	bytediv_init.name = clk_name;
>  	bytediv_init.ops = &clk_bytediv_ops;
> @@ -442,7 +442,7 @@ static int pll_28nm_register(struct dsi_pll_28nm
> *pll_28nm, struct clk_hw **prov
>  		return ret;
>  	provided_clocks[DSI_BYTE_PLL_CLK] = &bytediv->hw;
> 
> -	snprintf(clk_name, 32, "dsi%dpll", pll_28nm->phy->id);
> +	snprintf(clk_name, 32, "dsi%dpll", pll_28nm->phy->id + 1);
>  	/* DIV3 */
>  	hw = devm_clk_hw_register_divider(dev, clk_name,
>  				parent_name, 0, pll_28nm->phy->pll_base +