[PATCH] drm: bridge: icn6211: Fix DSI-to-DPI PLL configuration

[Maxime Ripard]

On Sat, Apr 02, 2022 at 02:41:18AM +0200, Marek Vasut wrote:
> The datasheet for this bridge is not available, the PLL behavior has been
> inferred from [1] and [2] and by analyzing the DPI pixel clock with scope.
> After further testing with other displays and different DSI data lane count,
> it turns out the P-factor is not 1/2^N divider, but rather only 1/N divider.
> It also turns out the input into the PLL seem to be ByteClock instead of DSI
> HS clock.
> 
> Rework the P-factor calculation such that the PLL calculation code handles
> P-factor from 1..32 with P-factors above 16 must be even. In case P-factor
> is even, enable built-in 1:2 divider and program P-factor/2 to PLL_REF_DIV,
> otherwise configure only the P-factor into PLL_REF_DIV register.
> 
> Switch the PLL factor calculation from kHz to Hz to maintain precision.
> 
> [1] https://github.com/rockchip-linux/kernel/blob/develop-4.19/drivers/gpu/drm/bridge/icn6211.c
> [2] https://github.com/tdjastrzebski/ICN6211-Configurator
> 
> Fixes: f30cf0ece691 ("drm: bridge: icn6211: Add generic DSI-to-DPI PLL configuration")
> Signed-off-by: Marek Vasut <marex at denx.de>
> Cc: Jagan Teki <jagan at amarulasolutions.com>
> Cc: Maxime Ripard <maxime at cerno.tech>
> Cc: Robert Foss <robert.foss at linaro.org>
> Cc: Sam Ravnborg <sam at ravnborg.org>
> Cc: Thomas Zimmermann <tzimmermann at suse.de>
> To: dri-devel at lists.freedesktop.org

Acked-by: Maxime Ripard <maxime at cerno.tech>

Maxime
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