[PATCH v2 12/17] drm/msm/dpu: move _dpu_plane_get_qos_lut to dpu_hw_util file
Dmitry Baryshkov
dmitry.baryshkov at linaro.org
Wed Apr 20 07:26:26 UTC 2022
On 20/04/2022 04:46, Abhinav Kumar wrote:
> _dpu_plane_get_qos_lut() is not specific to just dpu_plane.
> It can take any fill level and return the LUT matching it.
> This can be used even for other modules like dpu_writeback.
>
> Move _dpu_plane_get_qos_lut() to the common dpu_hw_util file
> and rename it to _dpu_hw_get_qos_lut().
>
> Signed-off-by: Abhinav Kumar <quic_abhinavk at quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov at linaro.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 25 +++++++++++++++++++++++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 4 ++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 27 +--------------------------
> 3 files changed, 30 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
> index aad8511..512316f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
> @@ -422,3 +422,28 @@ void dpu_hw_csc_setup(struct dpu_hw_blk_reg_map *c,
> DPU_REG_WRITE(c, csc_reg_off + 0x3c, data->csc_post_bv[1]);
> DPU_REG_WRITE(c, csc_reg_off + 0x40, data->csc_post_bv[2]);
> }
> +
> +/**
> + * _dpu_hw_get_qos_lut - get LUT mapping based on fill level
> + * @tbl: Pointer to LUT table
> + * @total_fl: fill level
> + * Return: LUT setting corresponding to the fill level
> + */
> +u64 _dpu_hw_get_qos_lut(const struct dpu_qos_lut_tbl *tbl,
> + u32 total_fl)
> +{
> + int i;
> +
> + if (!tbl || !tbl->nentry || !tbl->entries)
> + return 0;
> +
> + for (i = 0; i < tbl->nentry; i++)
> + if (total_fl <= tbl->entries[i].fl)
> + return tbl->entries[i].lut;
> +
> + /* if last fl is zero, use as default */
> + if (!tbl->entries[i-1].fl)
> + return tbl->entries[i-1].lut;
> +
> + return 0;
> +}
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
> index 3913475..529a6e0 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
> @@ -9,6 +9,7 @@
> #include <linux/io.h>
> #include <linux/slab.h>
> #include "dpu_hw_mdss.h"
> +#include "dpu_hw_catalog.h"
>
> #define REG_MASK(n) ((BIT(n)) - 1)
>
> @@ -324,4 +325,7 @@ void dpu_hw_csc_setup(struct dpu_hw_blk_reg_map *c,
> u32 csc_reg_off,
> const struct dpu_csc_cfg *data, bool csc10);
>
> +u64 _dpu_hw_get_qos_lut(const struct dpu_qos_lut_tbl *tbl,
> + u32 total_fl);
> +
> #endif /* _DPU_HW_UTIL_H */
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> index c77c3d9d..730f0a3 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> @@ -280,31 +280,6 @@ static int _dpu_plane_calc_fill_level(struct drm_plane *plane,
> }
>
> /**
> - * _dpu_plane_get_qos_lut - get LUT mapping based on fill level
> - * @tbl: Pointer to LUT table
> - * @total_fl: fill level
> - * Return: LUT setting corresponding to the fill level
> - */
> -static u64 _dpu_plane_get_qos_lut(const struct dpu_qos_lut_tbl *tbl,
> - u32 total_fl)
> -{
> - int i;
> -
> - if (!tbl || !tbl->nentry || !tbl->entries)
> - return 0;
> -
> - for (i = 0; i < tbl->nentry; i++)
> - if (total_fl <= tbl->entries[i].fl)
> - return tbl->entries[i].lut;
> -
> - /* if last fl is zero, use as default */
> - if (!tbl->entries[i-1].fl)
> - return tbl->entries[i-1].lut;
> -
> - return 0;
> -}
> -
> -/**
> * _dpu_plane_set_qos_lut - set QoS LUT of the given plane
> * @plane: Pointer to drm plane
> * @fb: Pointer to framebuffer associated with the given plane
> @@ -333,7 +308,7 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
> lut_usage = DPU_QOS_LUT_USAGE_MACROTILE;
> }
>
> - qos_lut = _dpu_plane_get_qos_lut(
> + qos_lut = _dpu_hw_get_qos_lut(
> &pdpu->catalog->perf.qos_lut_tbl[lut_usage], total_fl);
>
> trace_dpu_perf_set_qos_luts(pdpu->pipe - SSPP_VIG0,
--
With best wishes
Dmitry
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