[PATCH] drm/msm/dsi: use RMW cycles in dsi_update_dsc_timing
Dmitry Baryshkov
dmitry.baryshkov at linaro.org
Sat Apr 30 17:39:09 UTC 2022
On 30/04/2022 18:16, Abhinav Kumar wrote:
>
>
> On 4/30/2022 1:11 AM, Dmitry Baryshkov wrote:
>> The downstream uses read-modify-write for updating command mode
>> compression registers. Let's follow this approach. This also fixes the
>> following warning:
>>
>> drivers/gpu/drm/msm/dsi/dsi_host.c:918:23: warning: variable
>> 'reg_ctrl' set but not used [-Wunused-but-set-variable]
>>
>> Reported-by: kernel test robot <lkp at intel.com>
>> Fixes: 08802f515c3c ("drm/msm/dsi: Add support for DSC configuration")
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov at linaro.org>
>> ---
>> drivers/gpu/drm/msm/dsi/dsi_host.c | 4 +++-
>> 1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
>> b/drivers/gpu/drm/msm/dsi/dsi_host.c
>> index c983698d1384..a5619ad82a53 100644
>> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
>> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
>> @@ -961,10 +961,12 @@ static void dsi_update_dsc_timing(struct
>> msm_dsi_host *msm_host, bool is_cmd_mod
>> reg_ctrl = dsi_read(msm_host,
>> REG_DSI_COMMAND_COMPRESSION_MODE_CTRL);
>> reg_ctrl2 = dsi_read(msm_host,
>> REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2);
>> + reg_ctrl &= ~0xffff;
>> reg_ctrl |= reg;
>> + reg_ctrl &=
>> ~DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__MASK;
>
> Shoulnt this be
>
> reg_ctrl2 &= ~DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__MASK;
>
> You seem to have used reg_ctrl which is wrong.
>
Yes. Dummy c&p. I'll post v2 asap.
>> reg_ctrl2 |=
>> DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH(bytes_in_slice);
>> - dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL, reg);
>> + dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL,
>> reg_ctrl);
>> dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2,
>> reg_ctrl2);
>> } else {
>> dsi_write(msm_host, REG_DSI_VIDEO_COMPRESSION_MODE_CTRL, reg);
--
With best wishes
Dmitry
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