[PATCH v2] drm/i915/guc/slpc: Allow SLPC to use efficient frequency
Rodrigo Vivi
rodrigo.vivi at intel.com
Mon Aug 15 23:24:21 UTC 2022
On Mon, Aug 15, 2022 at 04:22:04PM -0700, Vinay Belgaumkar wrote:
> Host Turbo operates at efficient frequency when GT is not idle unless
> the user or workload has forced it to a higher level. Replicate the same
> behavior in SLPC by allowing the algorithm to use efficient frequency.
> We had disabled it during boot due to concerns that it might break
> kernel ABI for min frequency. However, this is not the case since
> SLPC will still abide by the (min,max) range limits.
>
> With this change, min freq will be at efficient frequency level at init
> instead of fused min (RPn). If user chooses to reduce min freq below the
> efficient freq, we will turn off usage of efficient frequency and honor
> the user request. When a higher value is written, it will get toggled
> back again.
>
> The patch also corrects the register which needs to be read for obtaining
> the correct efficient frequency for Gen9+.
>
> We see much better perf numbers with benchmarks like glmark2 with
> efficient frequency usage enabled as expected.
>
> v2: Address review comments (Rodrigo)
>
> BugLink: https://gitlab.freedesktop.org/drm/intel/-/issues/5468
>
> Cc: Rodrigo Vivi <rodrigo.vivi at intel.com>
> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar at intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_rps.c | 7 ++-
> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 66 ++++-----------------
> drivers/gpu/drm/i915/intel_mchbar_regs.h | 3 +
> 3 files changed, 22 insertions(+), 54 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
> index c7d381ad90cf..8c289a032103 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> @@ -1107,7 +1107,12 @@ void gen6_rps_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps *c
> caps->min_freq = (rp_state_cap >> 0) & 0xff;
> } else {
> caps->rp0_freq = (rp_state_cap >> 0) & 0xff;
> - caps->rp1_freq = (rp_state_cap >> 8) & 0xff;
> + if (GRAPHICS_VER(i915) >= 10)
> + caps->rp1_freq = REG_FIELD_GET(RPE_MASK,
> + intel_uncore_read(to_gt(i915)->uncore,
> + GEN10_FREQ_INFO_REC));
> + else
> + caps->rp1_freq = (rp_state_cap >> 8) & 0xff;
> caps->min_freq = (rp_state_cap >> 16) & 0xff;
> }
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> index e1fa1f32f29e..9d49ccef03bb 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> @@ -137,17 +137,6 @@ static int guc_action_slpc_set_param(struct intel_guc *guc, u8 id, u32 value)
> return ret > 0 ? -EPROTO : ret;
> }
>
> -static int guc_action_slpc_unset_param(struct intel_guc *guc, u8 id)
> -{
> - u32 request[] = {
> - GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST,
> - SLPC_EVENT(SLPC_EVENT_PARAMETER_UNSET, 1),
> - id,
> - };
> -
> - return intel_guc_send(guc, request, ARRAY_SIZE(request));
> -}
> -
> static bool slpc_is_running(struct intel_guc_slpc *slpc)
> {
> return slpc_get_state(slpc) == SLPC_GLOBAL_STATE_RUNNING;
> @@ -201,16 +190,6 @@ static int slpc_set_param(struct intel_guc_slpc *slpc, u8 id, u32 value)
> return ret;
> }
>
> -static int slpc_unset_param(struct intel_guc_slpc *slpc,
> - u8 id)
> -{
> - struct intel_guc *guc = slpc_to_guc(slpc);
> -
> - GEM_BUG_ON(id >= SLPC_MAX_PARAM);
> -
> - return guc_action_slpc_unset_param(guc, id);
> -}
> -
> static int slpc_force_min_freq(struct intel_guc_slpc *slpc, u32 freq)
> {
> struct drm_i915_private *i915 = slpc_to_i915(slpc);
> @@ -491,6 +470,16 @@ int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val)
>
> with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
>
> + /* Ignore efficient freq if lower min freq is requested */
> + ret = slpc_set_param(slpc,
> + SLPC_PARAM_IGNORE_EFFICIENT_FREQUENCY,
> + val < slpc->rp1_freq);
> + if (unlikely(ret)) {
> + i915_probe_error(i915, "Failed to toggle efficient freq (%pe)\n",
> + ERR_PTR(ret));
> + return ret;
> + }
> +
> ret = slpc_set_param(slpc,
> SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
> val);
> @@ -587,7 +576,9 @@ static int slpc_set_softlimits(struct intel_guc_slpc *slpc)
> return ret;
>
> if (!slpc->min_freq_softlimit) {
> - slpc->min_freq_softlimit = slpc->min_freq;
> + ret = intel_guc_slpc_get_min_freq(slpc, &slpc->min_freq_softlimit);
> + if (unlikely(ret))
> + return ret;
> slpc_to_gt(slpc)->defaults.min_freq = slpc->min_freq_softlimit;
> } else if (slpc->min_freq_softlimit != slpc->min_freq) {
> return intel_guc_slpc_set_min_freq(slpc,
> @@ -597,29 +588,6 @@ static int slpc_set_softlimits(struct intel_guc_slpc *slpc)
> return 0;
> }
>
> -static int slpc_ignore_eff_freq(struct intel_guc_slpc *slpc, bool ignore)
> -{
> - int ret = 0;
> -
> - if (ignore) {
> - ret = slpc_set_param(slpc,
> - SLPC_PARAM_IGNORE_EFFICIENT_FREQUENCY,
> - ignore);
> - if (!ret)
> - return slpc_set_param(slpc,
> - SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
> - slpc->min_freq);
> - } else {
> - ret = slpc_unset_param(slpc,
> - SLPC_PARAM_IGNORE_EFFICIENT_FREQUENCY);
> - if (!ret)
> - return slpc_unset_param(slpc,
> - SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ);
> - }
> -
> - return ret;
> -}
> -
> static int slpc_use_fused_rp0(struct intel_guc_slpc *slpc)
> {
> /* Force SLPC to used platform rp0 */
> @@ -679,14 +647,6 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
>
> slpc_get_rp_values(slpc);
>
> - /* Ignore efficient freq and set min to platform min */
> - ret = slpc_ignore_eff_freq(slpc, true);
> - if (unlikely(ret)) {
> - i915_probe_error(i915, "Failed to set SLPC min to RPn (%pe)\n",
> - ERR_PTR(ret));
> - return ret;
> - }
> -
> /* Set SLPC max limit to RP0 */
> ret = slpc_use_fused_rp0(slpc);
> if (unlikely(ret)) {
> diff --git a/drivers/gpu/drm/i915/intel_mchbar_regs.h b/drivers/gpu/drm/i915/intel_mchbar_regs.h
> index 2aad2f0cc8db..ffc702b79579 100644
> --- a/drivers/gpu/drm/i915/intel_mchbar_regs.h
> +++ b/drivers/gpu/drm/i915/intel_mchbar_regs.h
> @@ -196,6 +196,9 @@
> #define RP1_CAP_MASK REG_GENMASK(15, 8)
> #define RPN_CAP_MASK REG_GENMASK(23, 16)
>
> +#define GEN10_FREQ_INFO_REC _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5ef0)
> +#define RPE_MASK REG_GENMASK(15, 8)
> +
> /* snb MCH registers for priority tuning */
> #define MCH_SSKPD _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
> #define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
> --
> 2.35.1
>
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