[PATCH] drm/bridge: ps8640: Add double reset T4 and T5 to power-on sequence

[Hsin-Yi Wang]

On Thu, Aug 18, 2022 at 6:54 AM Doug Anderson <dianders at chromium.org> wrote:
>
> Hi,
>
> On Mon, Aug 15, 2022 at 2:39 AM Hsin-Yi Wang <hsinyi at chromium.org> wrote:
> >
> > The double reset power-on sequence is a workaround for the hardware
> > flaw in some chip that SPI Clock output glitch and cause internal MPU
> > unable to read firmware correctly. The sequence is suggested in ps8640
> > application note.
> >
> > Signed-off-by: Hsin-Yi Wang <hsinyi at chromium.org>
> > ---
> >  drivers/gpu/drm/bridge/parade-ps8640.c | 5 +++++
> >  1 file changed, 5 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c b/drivers/gpu/drm/bridge/parade-ps8640.c
> > index 49107a6cdac18..d7483c13c569b 100644
> > --- a/drivers/gpu/drm/bridge/parade-ps8640.c
> > +++ b/drivers/gpu/drm/bridge/parade-ps8640.c
> > @@ -375,6 +375,11 @@ static int __maybe_unused ps8640_resume(struct device *dev)
> >         gpiod_set_value(ps_bridge->gpio_reset, 1);
> >         usleep_range(2000, 2500);
> >         gpiod_set_value(ps_bridge->gpio_reset, 0);
> > +       /* Double reset for T4 and T5 */
> > +       msleep(50);
> > +       gpiod_set_value(ps_bridge->gpio_reset, 1);
> > +       msleep(50);
> > +       gpiod_set_value(ps_bridge->gpio_reset, 0);
>
> We really need another 100 ms here? ps8640 is already quite slow at
> powering itself up and that has a real user impact. Why was it only
> 2.5 ms for the first reset and 50 ms for the second?
>

The T4 and T5 are required by Parade. I'm wondering if they can
shorten the 200ms below:

/*
* Mystery 200 ms delay for the "MCU to be ready". It's unclear if
* this is truly necessary since the MCU will already signal that
* things are "good to go" by signaling HPD on "gpio 9". See
* _ps8640_wait_hpd_asserted(). For now we'll keep this mystery delay
* just in case.
*/
msleep(200);

Does this have to wait 200ms? Can it shorten to 100 due to the
additional 100ms from T4 and T5?

> -Doug